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參數(shù)資料
| 型號： | AD7321BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT+ SAR 2CHAN 14TSSOP |
| 標準包裝： | 96 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7321CBZ-ND - BOARD EVALUATION FOR AD7321 |
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Data Sheet
AD7321
Rev. B | Page 17 of 36
Figure 25 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (see Figure 26). The output
impedances of the source driving the VIN+ and VIN pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
CS
VIN+
SW2
A
B
VIN–
VREF
05399-
019
Figure 25. ADC Differential Configuration During Acquisition Phase
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
A
B
CS
VIN+
SW2
A
B
VIN–
VREF
05399-
020
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7321 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range
Full-Scale Range/8192 Codes
LSB Size
±10 V
20 V
2.441 mV
±5 V
10 V
1.22 mV
±2.5 V
5 V
0.61 mV
0 V to +10 V
10 V
1.22 mV
The ideal transfer characteristic for the AD7321 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7321 when straight binary
coding is selected is shown in Figure 28.
011...111
011...110
000...001
000...000
111...111
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
UNIPOLAR RANGE
AGND – 1LSB
ANALOG INPUT
ADC
CO
DE
100...010
100...001
100...000
05399-
021
Figure 27. Twos Complement Transfer Characteristic
111...111
111...110
111...000
011...111
–FSR/2 + 1LSB
AGND + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
UNIPOLAR RANGE
ANALOG INPUT
ADC
CO
DE
000...010
000...001
000...000
05399-
022
Figure 28. Straight Binary Transfer Characteristic
ANALOG INPUT STRUCTURE
The analog inputs of the AD7321 are configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 9). The AD7321 can accept true
bipolar input signals. On power-up, the analog inputs operate as
two single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7321 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
D
VDD
C2
R1
VIN0
VSS
C1
05399-
023
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
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