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參數(shù)資料
| 型號： | AD7376AN50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | +-15 V Operation Digital Potentiometer |
| 中文描述： | 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 128 POSITIONS, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 335K |
| 代理商： | AD7376AN50 |
AD7376
–9–
REV. 0
T able II.
D
(DE C)
R
WA
(
V
)
Output State
127
64
1
0
74
5035
9996
10035
Full-Scale
Midscale (
RS
= 0 Condition)
1 LSB
Zero-Scale
T he typical distribution of R
BA
from device to device matching
is process lot dependent having a
±
30% variation. T he
change
in RBA with temperature has a –300 ppm/
°
C temperature
coefficient.
PROGRAMMING T HE POT E NT IOME T E R DIVIDE R
Voltage Output Operation
T he digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminal
AB divided by the 128-position resolution of the potentiometer
divider. T he general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is:
V
W
(
D
) =
D
/128
×
V
AB
+
V
B
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resis-
tors, not the absolute value; therefore, the drift improves to
5 ppm/
°
C.
GND
V
DD
SDO
AD7376
7-BIT
SERIAL
REGISTER
D
Q
CK
7
R
7
SDI
CLK
CS
A
W
B
V
SS
SHDN
RS
SHDN
7-BIT
RDAC
LATCH
Figure 41. Block Diagram
DIGIT AL INT E RFACING
T he AD7376 contains a standard three-wire serial input control
interface. T he three inputs are clock (CLK ),
CS
and serial data
input (SDI). T he positive-edge sensitive CLK input requires
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be de-
bounced by a flip-flop or other suitable means. When
CS
is
taken active low the clock loads data into the serial register on
each positive clock edge, see T able III. T he last seven bits
clocked into the serial register will be transferred to the 7-bit
RDAC latch, see Figure 41. Extra data bits are ignored. T he
serial-data-output (SDO) pin contains an open drain n-channel
FET . T his output requires a pull-up resistor in order to transfer
data to the next package’s SDI pin. T his allows for daisy chain-
ing several RDACs from a single processor serial data line.
Clock period needs to be increased when using a pull-up resistor
to the SDI pin of the following device in the series. Capacitive
loading at the daisy chain node SDO-SDI between devices must
be accounted for to successfully transfer data. When daisy
chaining is used, the
CS
should be kept low until all the bits of
every package are clocked into their respective serial registers
insuring that the data bits are in the proper decoding location.
T his would require 14 bits of data when two AD7376 RDACs
are daisy chained. During shutdown (
SHDN
) the SDO output
pin is forced to the off (logic high state) to disable power dissi-
pation in the pull up resistor. See Figure 42 for equivalent SDO
output circuit schematic.
T able III. Input Logic Control T ruth T able
CLK
CS
RS
SHDN
Register Activity
L
L
H
H
Enables SR, enables SDO pin.
P
L
H
H
Shifts one bit in from the SDI
pin. T he seventh previously
entered bit is shifted out of the
SDO pin.
X
P
H
H
Loads SR data into 7-bit RDAC
latch.
X
H
H
H
No Operation.
X
X
L
H
Sets 7-bit RDAC latch to mid-
scale, wiper centered, and SDO
latch cleared.
X
H
P
H
Latches 7-bit RDAC latch to
40
H
.
X
H
H
L
Opens circuits resistor A–terminal,
connects W to B, turns off SDO
output transistor.
NOT E
P = positive edge, X = don’t care, SR = shift register.
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