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參數(shù)資料
型號: AD7392ARZ
廠商: Analog Devices Inc
文件頁數(shù): 18/20頁
文件大?。?/td> 0K
描述: IC DAC 12BIT PARALLEL 3V 20-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 37
設(shè)置時間: 60µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 500µW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC W
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 17k
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
AD7392/AD7393
Rev. C | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
01
121
-00
6
AD7392
TOP VIEW
(Not to Scale)
VDD 1
VREF
20
SHDN 2
VOUT
19
CS 3
AGND
18
RS 4
DGND
17
D0 5
D11
16
D1 6
D10
15
D2 7
D9
14
D3 8
D8
13
D4 9
D7
12
D5 10
D6
11
01
12
1-
007
AD7393
TOP VIEW
(Not to Scale)
NC = NO CONNECT
VDD 1
VREF
20
SHDN 2
VOUT
19
CS 3
AGND
18
RS 4
DGND
17
NC 5
D9
16
NC 6
D8
15
D0 7
D7
14
D1 8
D6
13
D2 9
D5
12
D3 10
D4
11
Figure 3. AD7392 Pin Configuration
Figure 4. AD7393 Pin Configuration
Table 4. AD7392 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
2
SHDN
Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin. When
SHDN = 0, CS strobes write new data into the DAC register.
3
CS
Chip Select Latch Enable, Active Low.
4
RS
Asynchronous Active Low Input. Resets the DAC register to 0.
5 to 16
D0 to D11
Parallel Input Data Bits. D11 is the MSB; D0 is the LSB.
17
DGND
Digital Ground.
18
AGND
Analog Ground.
19
VOUT
DAC Voltage Output.
20
VREF
DAC Reference Input. Establishes the DAC full-scale voltage.
Table 5. AD7393 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
2
SHDN
Power Shutdown Active Low Input. DAC register contents are saved as long as power stays on the VDD pin.
When SHDN = 0, CS strobes write new data into the DAC register.
3
CS
Chip Select Latch Enable, Active Low.
4
RS
Asynchronous Active Low Input. Resets the DAC register to 0.
5, 6
NC
No Connect.
7 to 16
D0 to D9
Parallel Input Data Bits. D9 is the MSB; D0 is the LSB.
17
DGND
Digital Ground.
18
AGND
Analog Ground.
19
VOUT
DAC Voltage Output.
20
VREF
DAC Reference Input. Establishes the DAC full-scale voltage.
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AD7392ARZ 制造商:Analog Devices 功能描述:IC 12-BIT DAC
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