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參數(shù)資料
| 型號： | AD7398WBRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD SRL-IN 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 16mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | * |
AD7398/AD7399
Rev. C | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
02179-
005
1
VOUTB
16
VOUTC
2
VOUTA
15
VOUTD
3
VSS
14
VDD
4
VREFA
13
VREFC
5
VREFB
12
VREFD
6
GND
11
SDI
7
LDAC
10
CLK
8
RS
9
CS
AD7398/
AD7399
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Table 5. Control Logic Truth Table
CS
CLK
LDAC
Serial Shift Register Function
Input Register Function
DAC Register
H
X
H
No effect
L
H
No effect
L
↑+
H
Shift register data advanced one bit
Latched
No effect
L
H
No effect
Latched
No effect
↑+
L/H
H
No effect
Updated with shift register contents
No effect
H
X
L
No effect
Latched
Transparent
H
X
↑+
No effect
Latched
NOTES
1.
↑+ = Positive logic transition; ↓– = Negative logic transition; X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all zeros.
3. During power shutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out
of shutdown mode.
4. The LDAC input is a level-sensitive input that controls the four DAC registers.
Pin No.
Mnemonic
Description
1
VOUTB
DAC B Voltage Output.
2
VOUTA
DAC A Voltage Output.
3
VSS
Negative Power Supply Input. Specified range of operation 0 V to 5.5 V.
4
VREFA
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin or VSS pin.
5
VREFB
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin or VSS pin.
6
GND
Ground Pin.
7
LDAC
Load DAC Register Strobe. Level sensitive active low. Transfers all input register data to DAC registers.
Asynchronous active low input. See Table 5 for operation.
8
RS
Resets Input and DAC Registers to All Zero Codes. Shift register contents unchanged.
9
CS
Chip Select. Active low input. Disables shift register loading when high. Transfers serial register data to the input
register when CS returns high. Does not effect LDAC operation.
10
CLK
Schmitt Triggered Clock Input. Positive edge clocks data into shift register.
11
SDI
Serial Data Input. Input data loads directly into the shift register.
12
VREFD
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin or VSS pin.
13
VREFC
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin or VSS pin.
14
VDD
Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.
15
VOUTD
DAC D Voltage Output.
16
VOUTC
DAC C Voltage Output.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7399 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, Serial-Input 12-Bit/10-Bit DACs |
| AD7399BR | 功能描述:IC DAC 10BIT QUAD SRL 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD7399BR | 制造商:Analog Devices 功能描述:CONVERTOR AD ((NW)) |
| AD7399BR-REEL | 功能描述:IC DAC 10BIT QUAD SRL 16-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD7399BR-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad, Serial-Input 12-Bit/10-Bit DACs |
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