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參數(shù)資料
| 型號(hào)： | AD7399 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad, Serial-Input 12-Bit/10-Bit DACs |
| 中文描述： | 四，串行輸入12-Bit/10-Bit數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 273K |
| 代理商： | AD7399 |
REV. 0
AD7398/AD7399
–13–
is limited by the internal buffer offset voltage and the output
drive current capability of the output stage. One should at least
budget the V
ZSE
offset voltage as the closest the output voltage
can get to either supply voltage under a no load condition. Under
a loaded output, degrade the headroom by a factor of 2 mV per
1 mA of load current. Also note that the internal op amp has an
offset voltage so that the first eight codes of AD7398 may not
respond at either the supply voltage or at ground until the internal
DAC voltage exceeds the output buffers offset voltage. Simi-
larly, the first two codes of AD7399 should not be used.
POWER SUPPLY SEQUENCING
V
DD
/V
SS
of AD7398/AD7399 should be powered from the system
analog supplies. In addition, V
IN
of the external reference should
also be coming from the same supply. Such practice will avoid
a possible latch-up when the reference is powered on prior to
V
DD
/V
SS
, or powered off subsequent to V
DD
/V
SS
. If V
DD
/V
SS
and V
REF
are separate power sources, then ensure V
DD
/V
SS
is
powered on before V
REF
and powered off after V
REF
. In addition,
V
REF
pins of the unused DACs should also be connected to GND
or some power sources to ensure similar power-up/-down sequence.
PROGRAMMABLE POWER SHUTDOWN
The two MSBs of the serial input register, SA and SD, are used
to program various shutdown modes. If SA is set to Logic 1, all
DACs will be in shutdown mode. If SA = 0 and SD = 1, a cor-
responding DAC will be shut down addressed by Bits A0 and
A1, See Tables II
–
IV.
WORST CASE ACCURACY
Assuming a perfect reference, the worst-case output voltage may
be calculated from the following equation.
V
D
N
2
V
(
V
V
INL
OUT
REF
FSE
ZSE
=
×
+
+
+
)
(3)
where
D
= Decimal Code Loaded to DAC Ranges 0
≤
D
≤
2
N
–
1
N
= Number of Bits
V
REF
= Applied Reference Voltage
V
FSE
= Full-Scale Error in Volts
V
ZSE
= Zero-Scale Error in Volts
INL
= Integral Nonlinearity in Volts INL is 0 at Full Scale
or Zero Scale
SERIAL DATA INTERFACE
The AD7398/AD7399 uses a 3-wire (
CS
, SDI, CLK) SPI-
compatible serial data interface. Serial data of the AD7398 and
AD7399 is clocked into the serial input register in a 16-bit and
14-bit data-word format respectively. MSB bits are loaded first.
Table II defines the 16 data-word bits for AD7398. Table III
defines the 14 data-word bits for the AD7399. Data is placed on
the SDI pin, and clocked into the register on the positive clock
edge of CLK subject to the data setup and data hold time
requirements specified in the Interface Timing specifications.
Data can only be clocked in while the
CS
chip select pin is
active low. For the AD7398, only the last 16 bits which are
clocked into the serial register, will be interrogated when the
CS
pin returns to the logic high state, extra data bits are ignored.
For the AD7399, only the last 14 bits, which are clocked into
the serial register, will be interrogated when the
CS
pin returns
to the logic high state. Since most microcontrollers
’
output
serial data is in 8-bit bytes, two right-justified data bytes can be
written to the AD7398 and AD7399. Keeping the
CS
line low
between the first and second bytes transfer will result in a suc-
cessful serial register update.
Once the data is properly aligned in the shift register, the posi-
tive edge of the
CS
initiates the transfer of new data to the target
DAC register, determined by the decoding of address Bits A1
and A0. For the AD7398, Tables I, II, IV, and Figures 2 and
3 define the characteristics of the software serial interface. For
the AD7399, Tables I, III, IV, and Figure 3 (with 14-bits excep-
tion) define the characteristics of the software serial interface.
Figures 6 and 7 show the equivalent logic interface for the key
digital control pins for AD7398 and AD7399.
An asynchronous
RS
provides hardware control reset to zero-
code state over the preset function and DAC Register loading. If
this function is not needed, the
RS
pin can be tied to logic high.
CLK
TO INPUT REGISTER
ADDRESS
DECODER
A
B
C
D
SHIFT REGISTER
SDI
CS
EN
Figure 6. Equivalent Logic Interface
POWER-ON RESET
When the V
DD
power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state. The V
DD
power supply should have a smooth positive
ramp without drooping in order to have consistent results,
especially in the region of V
DD
= 1.5 V to 2.2 V. The V
SS
sup-
ply has no effect on the power-on reset performance. The
DAC register data will stay at zero until a valid serial register
data load takes place.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
DD
as shown in Figure 7.
GND
DIGITAL INPUTS
V
DD
5k
Figure 7. Equivalent ESD Protection Circuits
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7398/AD7399 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data signal
and a synchronization signal. The AD7398/AD7399 requires a
16-bit/14-bit data word with data valid on the rising edge of CLK.
The DAC update may be done automatically when all the data
is clocked in, or it may be done under control of
LDAC
.
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