參數(shù)資料
型號(hào)： AD7399BR
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Quad, Serial-Input 12-Bit/10-Bit DACs
中文描述： SERIAL INPUT LOADING, 6 us SETTLING TIME, 10-BIT DAC, PDSO16
封裝： MS-013AA, WSOIC-16
文件頁數(shù)： 2/16頁
文件大?。?/td> 273K
代理商： AD7399BR
REV. 0
–2–
AD7398/AD7399–SPECIFICATIONS
AD7398 12-BIT VOLTAGE OUTPUT DAC
P
arameter
Symbol
Condition
3 V–5 V 10%
5 V 10%
Unit
STATIC PERFORMANCE
Resolution
1
Relative Accuracy
2
Differential Nonlinearity
2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco
3
N
INL
DNL
V
ZSE
V
FSE
TCV
FS
12
±
1.5
±
1
7
±
2.5
1.5
12
±
1.5
±
1
±
2.5
±
2.5
1.5
Bits
LSB max
LSB max
mV max
mV max
ppm/
°
C typ
Monotonic
Data = 000
H
Data = FFF
H
REFERENCE INPUT
V
REF
IN Range
4
Input Resistance
5
Input Capacitance
3
V
REF
R
REF
C
REF
0/V
DD
35
5
V
SS
/V
DD
35
5
V min/max
k
typ
6
pF typ
Data = 555
H
, Worst-Case
ANALOG OUTPUT
Output Current
Capacitive Load
3
I
OUT
C
L
Data = 800
H
,
V
OUT
= 4 LSB
No Oscillation
±
5
200
±
5
400
mA typ
pF max
LOGIC INPUTS
Logic Input Low Voltage
V
IL
V
DD
= 3 V
V
DD
= 5 V
CLK Only
0.5
0.8
80% V
DD
2.1–2.4
1
10
V max
V max
V min
V min
μ
A max
pF max
0.8
4.0
2.4
1
10
Logic Input High Voltage
V
IH
Input Leakage Current
Input Capacitance
3
I
IL
C
IL
INTERFACE TIMING
3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS
to Clock Set Up
Clock to
CS
Hold
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup to
CS
Load Hold to
CS
f
CLK
t
CH
t
CL
t
CSS
t
CSH
t
LDAC
t
DS
t
DH
t
LDS
t
LDH
11
45
45
10
20
45
15
10
0
20
16.6
30
30
5
15
30
10
5
0
15
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS
Output Slew Rate
Settling Time
8
Shutdown Recovery
DAC Glitch
Digital Feedthrough
Feedthrough
SR
t
S
t
SDR
Q
Q
DF
V
OUT
/V
REF
Data = 000
H
to FFF
H
to 000
H
To
±
0.1% of Full Scale
2
6
6
150
15
–63
2
6
6
150
15
–63
V/
μ
s typ
μ
s typ
μ
s typ
nVs typ
nVs typ
dB typ
Code 7FF
H
to 800
H
to 7FF
H
V
REF
= 1.5 V
DC
+ 1 V p-p,
Data = 000
H
, f = 100 kHz
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
I
DD_SD
I
DD
I
SS
P
DISS
PSS
No Load
V
IL
= 0 V, No Load
V
IL
= 0 V, No Load
V
IL
= 0 V, No Load
V
DD
=
±
5%
30/60
1.5/2.5
1.5/2.5
5
0.006
30/60
1.6/2.7
1.6/2.7
16
0.006
μ
A typ/max
mA typ/max
mA typ/max
mW typ
%/% max
NOTES
1
One LSB = V
REF
/4096 V for the 12-bit AD7398.
2
The first eight codes (000
H
, 007
H
) are excluded from the linearity error measurement in single supply operation.
3
These parameters are guaranteed by design and not subject to production testing.
4
When V
REF
is connected to either the V
DD
or the V
SS
power supply the corresponding V
OUT
voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the V
ZSE
error specification. See additional discussion in the Operation section of the data sheet.
5
Input resistance is code-dependent.
6
Typicals represent average readings measured at 25
°
C.
7
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8
The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
(@ V
DD
= 5 V, V
SS
= 0 V; or V
DD
= +5 V, V
SS
= –5 V, V
REF
= +2.5 V, –40 C < T
A
< +125 C, unless otherwise noted.)
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參數(shù)描述
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AD7399BRU-REEL 制造商:Analog Devices 功能描述:
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