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參數(shù)資料
| 型號(hào)： | AD7399BRU-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Quad, Serial-Input 12-Bit/10-Bit DACs |
| 中文描述： | SERIAL INPUT LOADING, 6 us SETTLING TIME, 10-BIT DAC, PDSO16 |
| 封裝： | 1.10 MM HEIGHT, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 273K |
| 代理商： | AD7399BRU-REEL7 |
REV. 0
AD7398/AD7399
–6–
Table I. Control Logic Truth Table
CS
CLK
LDAC
Serial Shift Register Function
Input Register Function
DAC Register
H
L
L
L
↑
+
H
H
X
L
↑
+
H
L/H
X
X
H
H
H
H
H
L
↑
+
No Effect
No Effect
Shift-Register-Data Advanced One Bit
No Effect
No Effect
No Effect
No Effect
No Effect
No Effect
Latched
Latched
Updated with SR Contents
Latched
Latched
No Effect
No Effect
Latched
Latched
Latched
Transparent
Latched
NOTES
1.
↑
+ Positive logic transition;
↓
– Negative logic transition; X Don’t Care; SR shift register.
2. At power ON, both the Input Register and the DAC Register are loaded with all zeros.
3
During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken
out of Shutdown mode.
4.
LDAC
input is a level-sensitive input that controls the four DAC registers.
Table II. AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
B15
SA
LSB
B0
D0
Bit Position
AD7398
B14
SD
B13
A1
B12
A0
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
NOTE
Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table III. AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
LSB
B0
D0
Bit Position
B13
AD7399
B12
SD
B11
A1
B10
A0
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
SA
NOTE
Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to
Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.
Table IV. AD7398/AD7399 Address Decode Control
SA
SD
A1
A0
DAC Channel Affected
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
All DACs Shutdown
DAC A Shutdown
DAC B Shutdown
DAC C Shutdown
DAC D Shutdown
DAC A Input Register Decoded
DAC B Input Register Decoded
DAC C Input Register Decoded
DAC D Input Register Decoded
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