參數(shù)資料
型號: AD745JR-16
廠商: Analog Devices Inc
文件頁數(shù): 12/12頁
文件大?。?/td> 0K
描述: IC OPAMP BIFET 20MHZ ULN 16SOIC
標(biāo)準(zhǔn)包裝: 47
放大器類型: J-FET
電路數(shù): 1
轉(zhuǎn)換速率: 12.5 V/µs
增益帶寬積: 20MHz
-3db帶寬: 20MHz
電流 - 輸入偏壓: 150pA
電壓 - 輸入偏移: 250µV
電流 - 電源: 8mA
電流 - 輸出 / 通道: 40mA
電壓 - 電源,單路/雙路(±): 9.6 V ~ 36 V,±4.8 V ~ 18 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 管件
REV. D
AD745
–9–
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of the
AD745 is a direct function of device junction temperature, IB
approximately doubling every 10
°C. Figure 9 shows the rela-
tionship between bias current and junction temperature for the
AD745. This graph shows that lowering the junction tempera-
ture will dramatically improve IB.
JUNCTION TEMPERATURE – C
10–6
–60
INPUT
BIAS
CURRENT
Amps
10–7
10–8
10–9
10–10
10–11
10–12
–40
–20
0
20
40
60
80
100
120
140
VS = 15V
TA = 25 C
Figure 9. Input Bias Current vs. Junction Temperature
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 10 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (
θ in °C/watt).
TA
JA
JC
CA
TJ
PIN
WHERE:
PIN = DEVICE DISSIPATION
TA = AMBIENT TEMPERATURE
TJ = JUNCTION TEMPERATURE
JC = THERMAL RESISTANCE – JUNCTION TO CASE
CA = THERMAL RESISTANCE – CASE TO AMBIENT
Figure 10. Device Thermal Model
From this model TJ = TA+
θJA PIN. Therefore, IB can be deter-
mined in a particular application by using Figure 9 together with
the published data for
θ
JA and power dissipation. The user can
modify
θJA by use of an appropriate clip-on heat sink such as the
Aavid #5801. Figure 11 shows bias current versus supply voltage
with
θ
JA as the third variable. This graph can be used to predict
bias current after
θJA has been computed. Again bias current will
double for every 10
°C.
SUPPLY VOLTAGE –
Volts
300
515
10
INPUT
BIAS
CURRENT
Amps
200
100
0
TA = 25 C
JA = 165 C/W
JA = 115 C/W
JA = 0 C/W
Figure 11. Input Bias Current vs. Supply Voltage for
Various Values of
θJA
A
(J TO DIE
MOUNT)
B
(DIE MOUNT
TO CASE)
A +
B =
JC
TJ
TA
CASE
Figure 12. Breakdown of Various Package Thermal
Resistance
REDUCED POWER SUPPLY OPERATION FOR
LOWER IB
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and, second, by reduc-
ing the basic gate-to-junction leakage (Figure 11). Figure 13
shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40
°C to
+85
°C temperature range. If the optional coupling capacitor,
C1, is used, this circuit will operate over the entire –55
°C to
+125
°C temperature range.
+5V
–5V
CT**
C1*
100
10k
108 **
CT
108
TRANSDUCER
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEE TEXT
AD745
Figure 13. A Piezoelectric Transducer
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