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參數(shù)資料
| 型號(hào)： | AD7476 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1MSPS,12-Bit ADCs in 6 Lead SOT-23(12位高速,低耗,逐次逼近式A/D轉(zhuǎn)換器) |
| 中文描述： | 6引腳SOT - 23（12位高速，低耗，逐次逼近式的A / D轉(zhuǎn)換器1MSPS ,12 -位ADC） |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | AD7476 |
AD7476/AD7477
–9–
REV. PrF
Prelimnary Technical Data
PRELMNARY
and hold will go back into track on the next SCLK rising
edge. On the 16th SCLK falling edge the SDAT A line
will go back into tristate . If the rising edge of
CS
occurs
before 16 SCLK s have elapsed then the conversion will be
terminated and the SDAT A line will go back into tri-
state, otherwise SDAT A returns to tri-state on the 16th
SCLK falling edge as shown in Figure 5 and Figure 6.
TECHNCAL
SCLK
CS
SDATA
INVALID DATA
VALID DATA
1
10
16
16
1
THE PART BEGINS
TO POWER UP
THE PART IS FULLY
POWERED UP
Figure 4. Exiting Power Down Mode
SE R IA L INT E R F A C E
Figure 5 and Figure 6 show the detailed timing diagram
for serial interfacing to the AD7476 and the AD7477 re-
spectively. T he serial clock provides the conversion clock
and also controls the transfer of information from the
AD7476/AD7477 during conversion.
CS
initiates the data transfer and conversion process. T he
falling edge of
CS
puts the track and hold into hold mode,
takes the bus out of tristate and the analog input is
sampled at this point. T he conversion is also initiated at
this point and will require 16 SCLK cycles to complete.
Once 13 SCLK falling edges have elapsed, then the track
Sixteen serial clock cycles are required to perform the
conversion process and to access data from the AD7476/
AD7477.
CS
going low provides the first leading zero to
be read in by the microcontroller or DSP. T he remaining
data is then clocked out by subsequent SCLK falling edges
beginning with the 2nd leading zero, thus the first falling
clock edge on the serial clock has the second leading zero
provided. T he final bit in the data transfer is valid on the
sixteenth falling edge, having being clocked out on the
previous (15th) falling edge. In applications with a slower
SCLK , it may be possible to read in data on each SCLK
rising edge, i.e. the first rising edge of SCLK after the
CS
falling edge would provide the first leading zero and the
15th risng SCLK edge would provide DB0.
Figure 5. AD7476 Serial Interface Timing Diagram
CS
SCLK
1
5
6
15
SDATA
4 LEADING ZERO'S
3-STATE
t
4
2
3
4
16
t
5
t
3
t
quiet
t
convert
t
2
3-STATE
DB11
DB10
DB9
DB0
t
6
t
9
t
8
14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7476A | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.35 V to 5.25 V, 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SC70 |
| AD7476AAKS-500RL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD7476AAKS-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 6-Pin SC-70 T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT SERL 6PIN SC-70 - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:12-BIT LOW POWER ADC IN SC70 PACKAGE I.C - Tape and Reel |
| AD7476AAKS-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Serial 6-Pin SC-70 T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT LOW POWER ADC IN SC70 PACKAGE - Tape and Reel |
| AD7476AAKSZ-500RL7 | 功能描述:IC ADC 12BIT 1MSPS LP SC70-6 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
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