VDD = 2.7 V to 5.25 V," />
參數(shù)資料
型號: AD7476ART-500RL7
廠商: Analog Devices Inc
文件頁數(shù): 24/25頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 1MSPS SOT-23-6
設(shè)計(jì)資源: Output Channel Monitoring Using AD5380 (CN0008)
AD5382 Channel Monitor Function (CN0012)
AD5381 Channel Monitor Function (CN0013)
AD5383 Channel Monitor Function (CN0015)
AD5390/91/92 Channel Monitor Function (CN0030)
Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 17.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-23-6
包裝: 剪切帶 (CT)
輸入數(shù)目和類型: 1 個單端,單極
配用: EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A
其它名稱: AD7476ART500RL7CT
AD7476/AD7477/AD7478
Rev. F | Page 7 of 24
AD7478 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, fSCLK = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
A Version1,2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 100 kHz sine wave, fSAMPLE = 1 MSPS
Signal-to-(Noise + Distortion) (SINAD)3
49
dB min
Total Harmonic Distortion (THD)3
65
dB max
Peak Harmonic or Spurious Noise (SFDR)3
65
dB max
Intermodulation Distortion (IMD)3
Second-Order Terms
68
dB typ
fa = 498.7 kHz, fb = 508.7 kHz
Third-Order Terms
68
dB typ
fa = 498.7 kHz, fb = 508.7 kHz
Aperture Delay
10
ns typ
Aperture Jitter
30
ps typ
Full Power Bandwidth
6.5
MHz typ
@ 3 dB
DC ACCURACY
Resolution
8
Bits
Integral Nonlinearity3
±0.5
LSB max
Differential Nonlinearity3
±0.5
LSB max
Guaranteed no missed codes to eight bits
Offset Error
±0.5
LSB max
Gain Error
±0.5
LSB max
Total Unadjusted Error (TUE)
±0.5
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to VDD
V
DC Leakage Current
±1
μA max
Input Capacitance
30
pF typ
LOGIC INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
VDD = 5 V
0.4
V max
VDD = 3 V
Input Current, IIN, SCLK Pin
±1
μA max
Typically 10 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
±1
μA typ
Input Capacitance, CIN4
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VDD 0.2
V min
ISOURCE = 200 μA, VDD = 2.7 V to 5.25 V
Output Low Voltage, VOL
0.4
V max
ISINK = 200 μA
Floating-State Leakage Current
±10
μA max
Floating-State Output Capacitance4
10
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
800
ns max
16 SCLK cycles with SCLK at 20 MHz
Track-and-Hold Acquisition Time
400
ns max
Throughput Rate
1
MSPS max
POWER REQUIREMENTS
VDD
2.7/5.25
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode (Static)
2
mA typ
VDD = 4.75 V to 5.25 V, SCLK on or off
1
mA typ
VDD = 2.7 V to 3.6 V, SCLK on or off
Normal Mode (Operational)
3.5
mA max
VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS
1.6
mA max
VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS
Full Power-Down Mode
1
μA max
SCLK off
80
μA max
SCLK on
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