參數(shù)資料
型號(hào)： AD7476AYKSZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/29頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 1MSPS SC70-6
設(shè)計(jì)資源： Output Channel Monitoring Using AD5380 (CN0008)
AD5382 Channel Monitor Function (CN0012)
AD5381 Channel Monitor Function (CN0013)
AD5383 Channel Monitor Function (CN0015)
AD5390/91/92 Channel Monitor Function (CN0030)
Power off protected data acquisition signal chain using ADG4612 , AD711, and AD7476 (CN0165)
標(biāo)準(zhǔn)包裝： 3,000
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝： SC-70-6
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
配用： EVAL-AD7476ACBZ-ND - BOARD EVALUATION FOR AD7476A
AD7476A/AD7477A/AD7478A
Rev. F | Page 19 of 28
SDATA
SCLK
CS
1
10
12
14
16
AD7476A/AD7477A/AD7478A
02930-020
VALID DATA
Figure 20. Normal Mode Operation
THREE-STATE
SDATA
SCLK
CS
1
10
12
14
16
2
02930-021
Figure 21. Entering Power-Down Mode
INVALID DATA
SDATA
SCLK
CS
1
10
12
14
16
A
1
16
VALID DATA
THE PART IS FULLY
POWERED UP WITH
VIN FULLY ACQUIRED
THE PART
BEGINS TO
POWER UP
02930-022
Figure 22. Exiting Power-Down Mode
When power supplies are first applied to the AD7476A/AD7477A/
AD7478A, the ADC can power up in either the power-down or
normal modes. Because of this, it is best to allow a dummy cycle
to elapse to ensure that the part is fully powered up before
attempting a valid conversion. Likewise, if it is intended to keep
the part in the power-down mode while not in use and the user
wishes the part to power up in power-down mode, the dummy
cycle can be used to ensure that the device is in power-down by
executing a cycle such as that shown in Figure 22. Once supplies
are applied to the AD7476A/AD7477A/AD7478A, the power-up
time is the same as that when powering up from the power-down
mode. It takes approximately 1 μs to power up fully if the part
powers up in normal mode. It is not necessary to wait 1 μs before
executing a dummy cycle to ensure the desired mode of operation.
Instead, a dummy cycle can occur directly after power is
supplied to the ADC. If the first valid conversion is performed
directly after the dummy conversion, care must be taken to
ensure that an adequate acquisition time has been allowed. As
mentioned earlier, when powering up from the power-down
mode, the part returns to track upon the first SCLK edge
applied after the falling edge of CS. However, when the ADC
initially powers up after supplies are applied, the track-and-hold
is already in track. This means, assuming one has the facility to
monitor the ADC supply current, if the ADC powers up in the
desired mode of operation and thus a dummy cycle is not
required to change the mode, a dummy cycle is not required to
place the track-and-hold into track.
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