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| 型號： | AD7476BRT |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +3.3V, 2.125Gbps/1.0625Gbps Fibre-Channel Port Bypass ICs |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | PLASTIC, MO-178AB, SOT-23, 6 PIN |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 360K |
| 代理商： | AD7476BRT |
REV. D
–3–
AD7477–SPECIFICATIONS
1
(V
DD
= 2.7 V to 5.25 V, f
SCLK
= 20 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
A Version
1, 2
S Version
1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
f
IN
= 100 kHz Sine Wave, f
SAMPLE
= 1 MSPS
61
–73
–74
61
–73
–74
dB min
dB max
dB max
–78
–78
10
30
6.5
–78
–78
10
30
6.5
dB typ
dB typ
ns typ
ps typ
MHz typ
fa = 103.5 kHz, fb = 113.5 kHz
fa = 103.5 kHz, fb = 113.5 kHz
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
10
±
1
±
0.9
±
1
±
1
10
±
1
±
0.9
±
1
±
1
Bits
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missed Codes to 10 Bits
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to V
DD
±
1
30
0 to V
DD
±
1
30
V
μ
A max
pF typ
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
2.4
0.8
0.4
±
1
±
1
10
2.4
0.8
0.4
±
1
±
1
10
V min
V max
V max
μ
A max
μ
A typ
pF max
V
DD
= 5 V
V
DD
= 3 V
Typically 10 nA, V
IN
= 0 V or V
DD
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
,
CS
Pin
Input Capacitance, C
IN4
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
4
Output Coding
V
DD
– 0.2
0.4
±
10
10
Straight (Natural) Binary
V
DD
– 0.2
0.4
±
10
10
V min
V max
μ
A max
pF max
I
SOURCE
= 200
μ
A; V
DD
= 2.7 V to 5.25 V
I
SINK
= 200
μ
A
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
Throughput Rate
800
400
1
800
400
1
ns max
ns max
MSPS max
16 SCLK Cycles with SCLK at 20 MHz
See Serial Interface Section
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
2.7/5.25
2.7/5.25
V min/max
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V; SCLK On or Off
V
DD
= 2.7 V to 3.6 V; SCLK On or Off
V
DD
= 4.75 V to 5.25 V; f
SAMPLE
= 1 MSPS
V
DD
= 2.7 V to 3.6 V; f
SAMPLE
= 1 MSPS
SCLK Off
SCLK On
2
1
3.5
1.6
1
80
2
1
3.5
1.6
1
80
mA typ
mA typ
mA max
mA max
μ
A max
μ
A max
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
5
Normal Mode (Operational)
17.5
4.8
5
17.5
4.8
5
mW max
mW max
μ
W max
V
DD
= 5 V; f
SAMPLE
= 1 MSPS
V
DD
= 3 V; f
SAMPLE
= 1 MSPS
V
DD
= 5 V; SCLK Off
Full Power-Down
NOTES
1
Temperature ranges as follows: A Version: –40
°
C to +85
°
C; S Version: –55
°
C to +125
°
C.
2
Operational from V
= 2.0 V, with input high voltage, V
INH
= 1.8 V min.
3
See Terminology section.
4
Guaranteed by characterization.
5
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
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