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參數(shù)資料
| 型號： | AD7476SRTZ-500RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | PLASTIC, LEAD FREE, MO-178AB, SOT-23, 6 PIN |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 360K |
| 代理商： | AD7476SRTZ-500RL7 |
REV. D
AD7476/AD7477/AD7478
–5–
TIMING SPECIFICATIONS
1, 2
(V
DD
= 2.35 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
AD7476/AD7477/AD7478
Parameter
f
SCLK4
3 V
3
5 V
3
Unit
Description
10
20
12
16
×
t
SCLK
50
10
20
12
16
×
t
SCLK
50
kHz min
MHz max
MHz max
A Version
B Version
t
CONVERT
t
QUIET
ns min
Minimum Quiet Time Required between Bus Relinquish and
Start of Next Conversion
Minimum
CS
Pulsewidth
CS
to SCLK Setup Time
Delay from
CS
until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge, A Version
Data Access Time after SCLK Falling Edge, B Version
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
t
1
t
2
t
35
t
45
10
10
20
40
70
0.4
×
t
SCLK
0.4
×
t
SCLK
10
10
25
1
10
10
20
20
20
0.4
×
t
SCLK
0.4
×
t
SCLK
10
10
25
1
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μ
s typ
t
5
t
6
t
7
t
86
t
POWER-UP7
NOTES
1
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
) and timed from a voltage level of 1.6 V.
2
A Version timing specifications apply to the AD7477 S Version and AD7478 S Version; B Version timing specifications apply to the AD7476 S Version.
3
3 V specifications apply from V
DD
= 2.7 V to 3.6 V for A Version; 3 V specifications apply from V
DD
= 2.35 V to 3.6 V for B Version; 5 V specifications apply from
V
= 4.75 V to 5.25 V.
4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
6
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the Timing Specifications is the true bus relinquish time
of the part and is independent of the bus loading.
7
See Power-Up Time section.
Specifications subject to change without notice.
200 A
I
OL
200 A
I
OH
C
L
50pF
TO OUTPUT
PIN
1.6V
Figure 1. Load Circuit for Digital Output Timing
Specifications
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相關代理商/技術(shù)參數(shù) |
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|---|---|
| AD7476SRTZ-500RL73 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7476SRTZ-EP-RL7 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 1MSPS Lo-Pwr RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD7476SRTZ-R2 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 1MSPS Lo-Pwr RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD7476SRTZ-R23 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23 |
| AD7476SRTZ-REEL | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12Bit 1MSPS Lo-Pwr RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
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