參數(shù)資料
型號(hào)： AD7477AARM-REEL7
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： +3.0V to +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
中文描述： 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： MO-187AA, MSOP-8
文件頁(yè)數(shù)： 17/20頁(yè)
文件大?。?/td> 360K
代理商： AD7477AARM-REEL7
REV. D
AD7476/AD7477/AD7478
–17–
AD7476/AD7477/AD7478 to DSP56xxx Interface
The connection diagram in Figure 20 shows how the AD7476/
AD7477/AD7478 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from Motorola.
The SSI is operated in Synchronous Mode (SYN bit in
CRB =1) with internally generated word frame sync for both
Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word
length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To
implement the Power-Down mode on the AD7476/AD7477/
AD7478, the word length can be changed to eight bits by setting
bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that
for signal processing applications, it is imperative that the
frame synchronization signal from the DSP56xxx provides
equidistant sampling.
SDATA
CS
SRD
SC2
AD7476/
AD7477/
AD7478
*
SCLK
DSP56xxx
*
SCK
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the DSP56xxx
AD7476/AD7477/AD7478 to MC68HC16 Interface
The Serial Peripheral Interface (SPI) on the MC68HC16 is
configured for Master Mode (MSTR = 1), the Clock Polarity
Bit (CPOL) = 1, and the Clock Phase Bit (CPHA) = 0. The SPI
is configured by writing to the SPI Control Register (SPCR)—see
the
68HC16
User Manual
. The serial transfer will take place as
a 16-bit operation when the SIZE bit in the SPCR register is set
to SIZE = 1. To implement the Power-Down mode with an
8-bit transfer, set SIZE = 0. A connection diagram is shown
in Figure 21.
SDATA
CS
MISO/PMC0
SS
/PMC3
AD7476/
AD7477/
AD7478
*
SCLK
MC68HC16
*
SCLK/PMC2
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. Interfacing to the MC68HC16
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