參數(shù)資料
型號: AD7477ARTZ-500RL7
廠商: Analog Devices Inc
文件頁數(shù): 6/25頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 1MSPS SOT23-6
標準包裝: 1
位數(shù): 10
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 17.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-23-6
包裝: 標準包裝
輸入數(shù)目和類型: 1 個單端,單極
產(chǎn)品目錄頁面: 778 (CN2011-ZH PDF)
配用: EVAL-AD7477CBZ-ND - BOARD EVALUATION FOR AD7477
其它名稱: AD7477ARTZ500RLDKR
AD7476/AD7477/AD7478
Rev. F | Page 13 of 24
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7476/AD7477/AD7478 are, respectively, 12-bit, 10-bit,
and 8-bit, fast, micropower, single-supply ADCs. The parts can
be operated from a 2.35 V to 5.25 V supply. When operated
from either a 5 V supply or a 3 V supply, the AD7476/AD7477/
AD7478 are capable of throughput rates of 1 MSPS when
provided with a 20 MHz clock.
Each AD7476/AD7477/AD7478 provides an on-chip, track-
and-hold ADC and a serial interface housed in a tiny 6-lead
SOT-23 package, which offers considerable space-saving
advantages. The serial clock input accesses data from the part
and provides the clock source for the successive-approximation
ADC. The analog input range is 0 V to VDD. An external
reference is not required for the ADC, nor is there a reference
on-chip. The reference for the AD7476/AD7477/AD7478 is
derived from the power supply and thus provides the widest
dynamic input range.
The AD7476/AD7477/AD7478 also feature a power-down
option to save power between conversions. The power-down
feature is implemented across the standard serial interface as
described in the Modes of Operation section.
CONVERTER OPERATION
The AD7476/AD7477/AD7478 are successive-approximation
analog-to-digital converters based around a charge redistribu-
tion DAC. Figure 1 and Figure 11 show simplified schematics
of the ADC. Figure 10 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A, the comparator
is held in a balanced condition, and the sampling capacitor
acquires the signal on VIN.
0102
4-
0
10
COMPARATOR
SAMPLING
CAPACITOR
ACQUISITION
PHASE
A
B
AGND
SW1
SW2
VIN
VDD/2
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
Figure 10. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 11), SW2 opens
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the charge redistri-
bution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 12 and Figure 13 show the ADC
transfer function.
01
02
4-
01
1
COMPARATOR
SAMPLING
CAPACITOR
CONVERSION
PHASE
A
B
AGND
SW1
SW2
VIN
VDD/2
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
Figure 11. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7476/AD7477/AD7478 is straight
binary. For the AD7476/AD7477, designed code transitions
occur midway between successive integer LSB values, such as
LSB, 1 LSB, and so on. The LSB size for the AD7476 is
VDD/4096, and the LSB size for the AD7477 is VDD/1024. The
ideal transfer characteristic for the AD7476/AD7477 is shown
For the AD7478, designed code transitions occur midway
between successive integer LSB values, such as 1 LSB, 2 LSB,
and so on. The LSB size for the AD7478 is VDD/256. The ideal
transfer characteristic for the AD7478 is shown in Figure 13.
0
102
4-
01
2
ANALOG INPUT
111 ... 111
0V
0.5LSB
+VDD – 1.5LSB
ADC
CO
DE
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
1LSB = VDD/4096 (AD7476)
1LSB = VDD/1024 (AD7477)
Figure 12. Transfer Characteristic for the AD7476/AD7477
010
24-
013
ANALOG INPUT
111 ... 111
0V
1LSB
+VDD – 1LSB
ADC
CO
DE
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
1LSB = VDD/256 (AD7478)
Figure 13. Transfer Characteristic for AD7478
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