參數(shù)資料
型號(hào)： AD7477SRT
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
中文描述： 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6
封裝： PLASTIC, MO-178AB, SOT-23, 6 PIN
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 360K
代理商： AD7477SRT
REV. D
–14–
AD7476/AD7477/AD7478
POWER VS. THROUGHPUT RATE
By using the Power-Down mode on the AD7476/AD7477/AD7478
when not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 14 shows how as the
throughput rate is reduced, the device remains in its power-down
state longer, and the average power consumption over time
drops accordingly.
For example, if the AD7476/AD7477/AD7478 is operated in a
continuous sampling mode with a throughput rate of 100 kSPS
and a SCLK of 20 MHz (V
DD
= 5 V), and the device is placed
in the Power-Down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 17.5 mW (V
DD
= 5 V). If the
power-up time is one dummy cycle, i.e., 1
μ
s, and the remaining
conversion time is another cycle, i.e., 1
μ
s, then the AD7476/
AD7477/AD7478 can be said to dissipate 17.5 mW for 2
μ
s
during each conversion cycle. If the throughput rate is 100 kSPS,
the cycle time is 10
μ
s and the average power dissipated
during each cycle is (2/10)
×
(17.5 mW) = 3.5 mW. If V
DD
=
3 V, SCLK = 20 MHz, and the device is again in Power-Down
mode between conversions, the power dissipation during normal
operation is 4.8 mW. The AD7476/AD7477/AD7478 can now
be said to dissipate 4.8 mW for 2
μ
s during each conversion
cycle. With a throughput rate of 100 kSPS, the average power
dissipated during each cycle is (2/10)
×
(4.8 mW) = 0.96 mW.
Figure 14 shows the power versus throughput rate when using
the Power-Down mode between conversions with both 5 V
and 3 V supplies.
THROUGHPUT RATE – kSPS
100
0
P
10
1
0.1
0.01
50
100
150
200
250
300
350
V
DD
= 5V, SCLK = 20MHz
V
DD
= 3V, SCLK = 20MHz
Figure 14. Power vs. Throughput Rate
The Power-Down mode is intended for use with throughput
rates of approximately 333 kSPS and under, because at higher
sampling rates power is not saved by using the Power-Down mode.
SERIAL INTERFACE
Figures 15, 16, and 17 show the detailed timing diagrams for
serial interfacing to the AD7476, AD7477, and AD7478,
respectively. The serial clock provides the conversion clock
and also controls the transfer of information from the AD7476/
AD7477/AD7478 during conversion.
The
CS
signal initiates the data transfer and conversion process.
The falling edge of
CS
puts the track-and-hold into Hold mode,
takes the bus out of three-state, and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require sixteenth SCLK cycles to complete. Once 13 SCLK
falling edges have elapsed, the track-and-hold will go back into
track on the next SCLK rising edge as shown in Figures 15, 16,
and 17 at Point B. On the sixteenth SCLK falling edge, the
SDATA line will go back into three-state. If the rising edge of
CS
occurs before 16 SCLKs have elapsed, the conversion will be
terminated and the SDATA line will go back into three-state;
otherwise, SDATA returns to three-state on the sixteenth SCLK
falling edge as shown in Figures 15, 16, and 17. Sixteen serial
clock cycles are required to perform the conversion process
and to access data from the AD7476/AD7477/AD7478.
CS
going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero. Thus the first falling clock edge on the serial clock
has the first leading zero provided and also clocks out the second
leading zero. The final bit in the data transfer is valid on the
sixteenth falling edge, having been clocked out on the previous
(fifteenth) falling edge. In applications with a slower SCLK, it
is possible to read in data on each SCLK rising edge, i.e., al-
though the first leading zero will have to be read on the first
SCLK falling edge after the
CS
falling edge. Therefore, the first
rising edge of SCLK after the
CS
falling edge will provide the
second leading zero and the fifteenth rising SCLK edge will have
DB0 provided or the final zero for the AD7477 and AD7478.
This may not work with most microcontrollers/DSPs, but could
possibly be used with FPGAs and ASICs.
相關(guān)PDF資料
PDF描述
AD7477SRT-500RL7 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7476SRTZ-REEL 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7476ARTZ-REEL7 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7476BRTZ-REEL7 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7476SRTZ-REEL7 1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7477SRT-500RL7 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
ad7477srt-r2 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述:10-BIT ADC IN SOT I.C. - Bulk
AD7477SRT-REEL 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7477SRT-REEL7 制造商:Rochester Electronics LLC 功能描述:10-BIT ADC IN SOT I.C. - Tape and Reel 制造商:Analog Devices 功能描述:
AD7477SRTZ-REEL 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10Bit 1MSPS Lo-Pwr RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類(lèi)型: 信噪比: 接口類(lèi)型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體:
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