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參數(shù)資料
| 型號： | AD7478AAKSZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:3; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Square Flange Receptacle; Body Style:Straight |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6 |
| 封裝： | ROHS COMPLIANT, MO-203AB, SC-70, 6 PIN |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 580K |
| 代理商： | AD7478AAKSZ-REEL |
REV. C
–6–
AD7476A/AD7477A/AD7478A
TIMING SPECIFICATIONS
1
(V
DD
= 2.35 V to 5.25 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
AD7476A/AD7477A/AD7478A
Parameter
f
SCLK 2
Unit
kHz min
3
kHz min
3
MHz max
Description
10
20
20
16 t
SCLK
14 t
SCLK
12 t
SCLK
50
A, B Grades
Y Grade
t
CONVERT
AD7476A
AD7477A
AD7478A
Minimum Quiet Time Required between Bus Relinquish
and Start of Next Conversion
Minimum
CS
Pulse Width
CS
to SCLK Setup Time
Delay from
CS
until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold Time
V
DD
≤
3.3 V
3.3 V < V
DD
≤
3.6 V
V
DD
> 3.6 V
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
t
QUIET
ns min
t
1
t
2
t
34
t
44
t
5
t
6
t
75
10
10
22
40
0.4 t
SCLK
0.4 t
SCLK
ns min
ns min
ns max
ns max
ns min
ns min
10
9.5
7
36
See Note 7
1
ns min
ns min
ns min
ns max
ns min
μ
s max
t
86
t
POWER-UP8
NOTES
1
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/space ratio for the SCLK input is 40/60 to 60/40.
3
Minimum f
at which specifications are guaranteed.
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 1.8 V when V
DD
= 2.35 V and 0.8 V or 2.0 V for V
DD
> 2.35 V.
5
Measured with 50 pF load capacitor.
6
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7
t
values also apply to t
minimum values.
8
See Power-Up Time section.
Specifications subject to change without notice.
TO OUTPUT
PIN
C
L
50pF
200 A
I
OH
200 A
I
OL
1.6V
Figure 1. Load Circuit for Digital Output Timing Specifications
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