參數(shù)資料
型號(hào)： AD7478AAKSZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT 1MSPS SC70-6 T/R
標(biāo)準(zhǔn)包裝： 10,000
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP，SC-88，SOT-363
供應(yīng)商設(shè)備封裝： SC-70-6
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
AD7476A/AD7477A/AD7478A
Rev. F | Page 20 of 28
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7476A/AD7477A/
AD7478A when not converting, the average power consump-
tion of the ADC decreases at lower throughput rates. Figure 23
shows that as the throughput rate is reduced, the device remains
in its power-down state longer and the average power consumption
over time drops accordingly.
For example, if the AD7476A/AD7477A/AD7478A operate in a
continuous sampling mode with a throughput rate of 100 kSPS
and an SCLK of 20 MHz (VDD = 5 V) and the devices are placed
in the power-down mode between conversions, the power
consumption is calculated as follows:
The power dissipation during normal operation is 17.5 mW
(VDD = 5 V). If the power-up time is one dummy cycle, that is,
1 μs, and the remaining conversion time is another cycle, that is,
1 μs, then the AD7476A/AD7477A/AD7478A dissipate 17.5 mW
for 2 μs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 μs, then
the average power dissipated during each cycle is (2/10) ×
(17.5 mW) = 3.5 mW.
If VDD = 3 V, SCLK = 20 MHz, and the devices are again in
power-down mode between conversions, then the power
dissipation during normal operation is 5.1 mW. Thus, the
AD7576A/AD7477A/AD8478A dissipate 5.1 mW for 2 μs
during each conversion cycle. With a throughput rate of
100 kSPS, the average power dissipated during each cycle is
(2/10) × (5.1 mW) = 1.02 mW.
Figure 23 shows the power vs. the throughput rate when using
the power-down mode between conversions with both 5 V and
3 V supplies. The power-down mode is intended for use with
throughput rates of approximately 333 kSPS or less, because at
higher sampling rates, the power-down mode produces no
power savings.
THROUGHPUT (kSPS)
100
0.1
0
POWER
(mW)
10
1
0.01
50
100
150
200
250
300
350
VDD = 5V, SCLK = 20MHz
VDD = 3V, SCLK = 20MHz
02930-023
Figure 23. Power vs. Throughput
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