VDD
參數(shù)資料
型號(hào)： AD7478ARTZ-500RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/25頁(yè)
文件大小： 0K
描述： IC ADC 8BIT 1MSPS LP SOT23-6
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 8
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 17.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
AD7476/AD7477/AD7478
Rev. F | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
01
02
4-
00
3
1
VDD
6
CS
2
GND
5
SDATA
3
VIN
4
SCLK
AD7476/
AD7477/
AD7478
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. The VDD range for the AD7476/AD7477/AD7478 is from 2.35 V to 5.25 V.
2
GND
Analog Ground. Ground reference point for all circuitry on the part. All analog input signals should be referred to this
GND voltage.
3
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
4
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as
the clock source for the AD7476/AD7477/AD7478 conversion process.
5
SDATA
Data Out. Logic output. The conversion result is provided on this output as a serial data stream. The bits are clocked
out on the falling edge of the SCLK input. The data stream from the AD7476 consists of four leading zeros followed by
the 12 bits of conversion data; this is provided MSB first. The data stream from the AD7477 consists of four leading
zeros followed by the 10 bits of conversion data, followed by two trailing zeros, which is also provided MSB first. The
data stream from the AD7478 consists of four leading zeros followed by the eight bits of conversion data, followed by
four trailing zeros, which is provided MSB first.
6
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7476/AD7477/AD7478 and framing the serial data transfer.
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