參數(shù)資料
型號: AD7482
廠商: Analog Devices, Inc.
元件分類: ADC
英文描述: 3MSPS, 12-Bit SAR ADC
中文描述: 3MSPS,12位SAR ADC
文件頁數(shù): 13/16頁
文件大小: 1498K
代理商: AD7482
REV. 0
AD7482
–13–
Typical Connection
Figure 13 shows a typical connection diagram for the AD7482
operating in Parallel Mode 1. Conversion is initiated by a falling
edge on
CONVST
. Once
CONVST
goes low, the
BUSY
signal
goes low, and at the end of conversion, the rising edge of
BUSY
is used to activate an interrupt service routine. The
CS
and
RD
lines are then activated to read the 12 data bits (13 bits if using
the overrange feature).
In Figure 13, the V
DRIVE
Pin is tied to DV
DD
, which results in logic
output levels being either 0 V or DV
DD
. The voltage applied
to V
DRIVE
controls the voltage value of the output logic signals.
For example, if DV
DD
is supplied by a 5 V supply and V
DRIVE
by
a 3 V supply, the logic output levels would be either 0 V or 3 V.
This feature allows the AD7482 to interface to 3 V devices, while
still enabling the ADC to process signals at a 5 V supply.
C/ P
RESET
MODE1
MODE2
WRITE
CLIP
NAP
STBY
PARALLEL
INTERFACE
D0–D12
CS
CONVST
RD
BUSY
C
BIAS
REFSEL
REFIN
REFOUT
VIN
AD7482
ADM809
V
DRIVE
DV
DD
AV
DD
0.1 F
DIGITAL
SUPPLY
4.75V–5.25V
10 F
1nF
+
0.1 F
0.1 F
+
47 F
ANALOG
SUPPLY
4.75V–5.25V
0V TO 2.5V
1nF
0.47 F
0.47 F
AD780 2.5V
REFERENCE
Figure 13. Typical Connection Diagram
Board Layout and Grounding
To obtain optimum performance from the AD7482, it is recom-
mended that a printed circuit board with a minimum of three
layers be used. One of these layers, preferably the middle layer,
should be as complete a ground plane as possible to give the
best shielding. The board should be designed in such a way that
the analog and digital circuitry is separated and confined to
certain areas of the board. This practice, along with avoiding
running digital and analog lines close together, should help to
avoid coupling digital noise onto analog lines.
The power supply lines to the AD7482 should be approxi-
mately 3 mm wide to provide low impedance paths and
reduce the effects of glitches on the power supply lines. It is
vital that good decoupling also be present. A combination of
ferrites and decoupling capacitors should be used as shown in
Figure 13. The decoupling capacitors should be as close to the
supply pins as possible. This is made easier by the use of multi-
layer boards. The signal traces from the AD7482 pins can be
run on the top layer, while the decoupling capacitors and
ferrites can be mounted on the bottom layer where the power
traces exist. The ground plane between the top and bottom
planes provide excellent shielding.
Figures 14a to 14e show a sample layout of the board area
immediately surrounding the AD7482. Pin 1 is the bottom left
corner of the device. Figure 14a shows the top layer where the
AD7482 is mounted with vias to the bottom routing layer high-
lighted. Figure 14b shows the bottom layer where the power
routing is with the same vias highlighted. Figure 14c shows the
bottom layer silkscreen where the decoupling components are
soldered directly beneath the device. Figure 14d shows the
silkscreen overlaid on the solder pads for the decoupling compo-
nents, and Figure 14e shows the top and bottom routing layers
overlaid. The black area in each figure indicates the ground
plane present on the middle layer.
Figure 14e
Figure 14a
Figure 14c
Figure 14b
Figure 14d
C1–6: 100 nF, C7–8: 470 nF, C9: 1 nF
L1–4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2)
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PDF描述
AD7482AST 3MSPS, 12-Bit SAR ADC
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