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參數(shù)資料
| 型號： | AD7482AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3MSPS, 12-Bit SAR ADC |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 1498K |
| 代理商： | AD7482AST |
REV. 0
AD7482
–3–
Parameter
Specification
Unit
Test Conditions/Comments
POWER REQUIREMENTS
V
DD
V
DRIVE
5
2.7
5.25
V
V min
V max
±
5%
I
DD
Normal Mode (Static)
Normal Mode (Operational)
NAP Mode
Standby Mode
12
18
0.5
2
0.5
mA max
mA max
mA max
μ
A max
μ
A typ
CS
and
RD
= Logic 1
Power Dissipation
Normal Mode (Operational)
NAP Mode
Standby Mode
6
90
2.5
10
mW max
mW max
μ
W max
NOTES
1
Temperature range is as follows:
–
40
°
C to +85
°
C.
2
SNR and SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB.
3
See Typical Performance Characteristics section for analog input circuits used.
4
See Terminology section.
5
Sample tested @ 25
°
C to ensure compliance.
6
Digital input levels at GND or V
DRIVE
.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
*
(V
DD
= 5 V
±
5%, AGND = DGND = 0 V, V
= External; all specifications T
MIN
to T
MAX
and valid for
V
DRIVE
= 2.7 V to 5.25 V, unless otherwise noted.)
(V
DD
= 5 V
±
5%, AGND = DGND = 0 V, V
REF
= External, f
SAMPLE
= 3 MSPS; all specifications T
MIN
to T
MAX
and valid for V
DRIVE
= 2.7 V to 5.25 V, unless otherwise noted.)
SPECIFICATIONS
(continued)
Parameter
Symbol
Min
Typ
Max
Unit
DATA READ
Conversion Time
Quiet Time before Conversion Start
CONVST
Pulsewidth
CONVST
Falling Edge to
BUSY
Falling Edge
CS
Falling Edge to
RD
Falling Edge
Data Access Time
CONVST
Falling Edge to New Data Valid
BUSY
Rising Edge to New Data Valid
Bus Relinquish Time
RD
Rising Edge to
CS
Rising Edge
CS
Pulsewidth
RD
Pulsewidth
t
CONV
t
QUIET
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
14
t
15
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
5
20
0
25
30
5
10
0
30
30
DATA WRITE
WRITE Pulsewidth
Data Setup Time
Data Hold Time
CS
Falling Edge to WRITE Falling Edge
WRITE Falling Edge to
CS
Rising Edge
t
9
t
10
t
11
t
12
t
13
5
2
6
5
0
ns
ns
ns
ns
ns
*
All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used.
Specifications subject to change without notice.
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