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參數(shù)資料
| 型號(hào)： | AD7482BST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 1.5Gbps Serial ATA-Compatible Mux/Buffer with Loopback and Equalization |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 1498K |
| 代理商： | AD7482BST |
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REV. 0
AD7482
–9–
CIRCUIT DESCRIPTION
C
ONVERTER OPERATION
The AD7482 is a 12-bit algorithmic successive-approximation
analog-to-digital converter based around a capacitive DAC. It
provides the user with track-and-hold, reference, an A/D con-
verter, and versatile interface logic functions on a single chip.
The normal analog input signal range that the AD7482 can
convert is 0 V to 2.5 V. By using the offset and overrange fea-
tures on the ADC, the AD7482 can convert analog input signals
from
–
200 mV to +2.7 V while operating from a single 5 V
supply. The part requires a 2.5 V reference, which can be
provided from the part
’
s own internal reference or an exter-
nal reference source. Figure 3 shows a very simplified
schematic of the ADC. The control logic, SAR, and capaci-
tive DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back to a balanced condition.
CAPACITIVE
DAC
SWITCHES
V
IN
V
REF
SAR
CONTROL
LOGIC
CONTROL
INPUTS
OUTPUT DATA
12-BIT PARALLEL
COMPARATOR
Figure 3. Simplified Block Diagram of AD7482
Conversion is initiated on the AD7482 by pulsing the
CONVST
input. On the falling edge of
CONVST
, the track-and-hold
goes from track mode to hold mode and the conversion
sequence is started. Conversion time for the part is 300 ns.
Figure 4 shows the ADC during conversion. When conversion
starts, SW2 will open and SW1 will move to Position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive-approximation routine and brings the
comparator back into a balanced condition. When the compara-
tor is rebalanced, the conversion result is available in the
SAR Register.
CAPACITIVE
DAC
COMPARATOR
CONTROL LOGIC
+
–
SW1
SW2
AGND
V
IN
A
B
Figure 4. ADC Conversion Phase
At the end of conversion, the track-and-hold returns to track mode
and the acquisition time begins. The track-and-hold acquisition
time is 40 ns. Figure 5 shows the ADC during its acquisition
phase. SW2 is closed and SW1 is in Position A. The comparator
is held in a balanced condition and the sampling capacitor
acquires the signal on V
IN
.
CAPACITIVE
DAC
COMPARATOR
CONTROL LOGIC
+
–
SW1
SW2
AGND
V
IN
A
B
Figure 5. ADC Acquisition Phase
ADC TRANSFER FUNCTION
The output coding of the AD7482 is straight binary. The designed
code transitions occur midway between the successive integer
LSB values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size
is V
REF
/4096. The nominal transfer characteristic for the AD7482
is shown in Figure 6. This transfer characteristic may be shifted
as detailed in the Offset/Overrange section.
000...000
0V
A
ANALOG INPUT
111...111
111...110
000...001
000...010
111...000
011...111
0.5LSB
+V
REF
– 1.5LSB
1LSB = V
REF
/4096
Figure 6. AD7482 Transfer Characteristic
POWER SAVING
The AD7482 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition to
this, the AD7482 features two power saving modes, NAP and
Standby. These modes are selected by bringing either the NAP or
STBY Pin to a logic high, respectively.
When operating the AD7482 in normal fully powered mode, the
current consumption is 18 mA during conversion and the quies-
cent current is 12 mA. Operating at a throughput rate of 1 MSPS,
the conversion time of 300 ns contributes 27 mW to the overall
power dissipation.
(
For the remaining 700 ns of the cycle, the AD7482 dissipates
42 mW of power.
(
300
1
/
μ
5
18
27
ns
s
V
mA
mW
)
×
×
(
)
=
700
1
/
μ
5
12
42
ns
s
V
mA
mW
)
×
×
(
)
=
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| AD7482BSTZ | 功能描述:IC ADC 12BIT SAR 3MSPS 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6 |
| AD7484 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:3MSPS, 14-Bit SAR ADC |
| AD7484BST | 制造商:Analog Devices 功能描述:ADC Single SAR 3Msps 14-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14 BIT 3.0 MEG ADC IC - Tape and Reel 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD7484BSTZ | 功能描述:IC ADC 14BIT SAR 3MSPS 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6 |
| AD7484BSTZ | 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
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