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| 型號(hào)： | AD75019JPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWIT 16X16 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 16:16 |
| 導(dǎo)通狀態(tài)電阻： | 300 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±12 V |
| 電流 - 電源： | 800µA |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
REV. C
AD75019
–3–
(TA = TMIN to TMAX, rated power supplies unless otherwise noted)
TIMING CHARACTERISTICS
1
Parameter
Symbol
Value
Units
Condition
Data Setup Time
t1
20
ns
min
SCLK Pulsewidth
t2
100
ns
min
Data Hold Time
t3
40
ns
min
SCLK Pulse Separation
t4
100
ns
min
SCLK to PCLK Delay
t5
65
ns
min
SCLK to PCLK Delay and Release
(t5 + t6)
5
ms
max
PCLK Pulsewidth
t6
65
ns
min
Propagation Delay, PCLK to Switches On or Off
_
70
ns
max
Data Load Time
_
52
s
SCLK = 5 MHz
SCLK Frequency
_
20
kHz
min
SCLK, PCLK Rise and Fall Times
_
1
s
max
NOTES
1Timing measurement reference level is 1.5 V.
Specifications subject to change without notice.
OPERATION TRUTH TABLE
Control Lines
PCLK
SCLK
SIN
SOUT
Operation/Comment
1
0
X
No operation.
1
Datai
Datai-256
The data on the SIN line is loaded into the serial register; data clocked into the
serial register 256 clocks ago appears at the SOUT output.
0
X
Data in the serial shift register transfers into the parallel latches which control the
switch array.
APPLICATIONS INFORMATION
Loading Data
Data to control the switches is clocked serially into a 256-bit
shift register and then transferred in parallel to 256 bits of mem-
ory. The rising edge of SCLK, the serial clock input, loads data
into the shift register. The first bit loaded via SIN, the serial
data input, controls the switch at the intersection of row Y15
and column X15. The next bits control the remaining columns
(down to X0) of row Y15, and are followed by the bits for row
Y14, and so on down to the data for the switch at the intersec-
tion of row Y0 and column X0. The shift register is dynamic, so
there is a minimum clock rate, specified as 20 kHz.
After the shift register is filled with the new 256 bits of control
data, PCLK is activated (pulsed low) to transfer the data to the
parallel latches. Since the shift register is dynamic, there is a
maximum time delay specified before the data is lost: PCLK
must be activated and brought back high within 5 ms after fill-
ing the shift register. The switch control latches are static and
will hold their data as long as power is applied.
To extend the number of switches in the array, you may cascade
multiple AD75019s. The SOUT output is the end of the shift
register, and may be directly connected to the SIN input of the
next AD75019.
Power Supply Sequencing and Bypassing
All junction-isolated parts operating on multiple power supplies
require proper attention to supply sequencing. Because BiMOS
II is a junction-isolated process, parasitic diodes exist between
VDD and VCC, and between VSS and DGND. As a result, VDD
must always be greater than (VCC – 0.5 V), and VSS must always
be less than (DGND + 0.5 V).
If you can’t ensure that system power supplies will sequence to
meet these conditions, external Schottky (e.g., 1N5818) or
silicon (e.g., 1N4001) diodes may be used. To protect the posi-
tive side, the anode would connect to VCC (Pin 42) and the
cathode to VDD (Pin 41). For the negative side, connect the
anode to VSS (Pin 4) and the cathode to DGND (Pin 43).
Each of the three power supply pins [VDD (Pin 41), VCC (Pin
42) and VSS (Pin 4)] should be bypassed to DGND (Pin 43)
through a 0.1
F ceramic capacitor located close to the package
pins.
Transistor Count
AD75019 contains 5,472 transistors. This number may be used
for calculating projected reliability.
TIMING DIAGRAM
Y0–X0
Y15–X14
t6
Y15–X15
t2
1
0
1
0
SCLK
PCLK
1 = CLOSE
0 = OPEN
SIN
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t5
t1
t3
t4
LOAD DATA INTO
SERIAL REGISTER
DURING RISING EDGE
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