AD7528–SPECIFICATIONS (V REF A = V
參數(shù)資料
型號(hào)： AD7528LRZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/8頁(yè)
文件大?。?/td> 0K
描述： IC DAC 8BIT DUAL MULTIPLY 20SOIC
標(biāo)準(zhǔn)包裝： 37
設(shè)置時(shí)間： 400ns
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
REV. B
–2–
AD7528–SPECIFICATIONS (V
REF A = VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
VDD = +5 V
VDD = +15 V
Parameter
Version
1
TA = +25
°CT
MIN, TMAX
TA= +25
°CT
MIN, TMAX
Units
Test Conditions/Comments
STATIC PERFORMANCE
2
Resolution
All
8
Bits
Relative Accuracy
J, A, S
± 1
LSB max
This is an Endpoint Linearity Specification
K, B, T
± 1/2
LSB max
L, C, U
± 1/2
LSB max
Differential Nonlinearity
All
± 1
LSB max
All Grades Guaranteed Monotonic Over
Full Operating Temperature Range
Gain Error
J, A, S
± 4
± 6
± 4
± 5
LSB max
Measured Using Internal RFB A and RFB B
K, B, T
± 2
± 4
± 2
± 3
LSB max
Both DAC Latches Loaded with 11111111
L, C, U
± 1
± 3
± 1
LSB max
Gain Error is Adjustable Using Circuits
of Figures 4 and 5
Gain Temperature Coefficient
3
Gain/Temperature
All
± 0.007
± 0.0035
%/
°C max
Output Leakage Current
OUT A (Pin 2)
All
± 50
± 400
± 50
± 200
nA max
DAC Latches Loaded with 00000000
OUT B (Pin 20)
All
± 50
± 400
± 50
± 200
nA max
Input Resistance (VREF A, VREF B)
All
8
k
min
Input Resistance TC = –300 ppm/
°C, Typical
15
k
max
Input Resistance is 11 k
VREF A/VREF B Input Resistance
Match
All
± 1
± 1% max
DIGITAL INPUTS4
Input High Voltage
VIH
All
2.4
13.5
V min
Input Low Voltage
VIL
All
0.8
1.5
V max
Input Current
IIN
All
± 1
± 10
± 1
± 10
A max
VIN = 0 or VDD
Input Capacitance
DB0–DB7
All
10
pF max
WR, CS, DAC A/DAC B
All
15
pF max
SWITCHING CHARACTERISTICS3
See Timing Diagram
Chip Select to Write Set Up Time
tCS
All
90
100
60
80
ns min
Chip Select to Write Hold Time
tCH
All
0
10
15
ns min
DAC Select to Write Set Up Time
tAS
All
90
100
60
80
ns min
DAC Select to Write Hold Time
tAH
All
0
10
15
ns min
Data Valid to Write Set Up Time
tDS
All
80
90
30
40
ns min
Data Valid to Write Hold Time
tDH
All
0
ns min
Write Pulsewidth
tWR
All
90
100
60
80
ns min
POWER SUPPLY
See Figure 3
IDD
All
2
mA max
All Digital Inputs VIL or VIH
All
100
500
100
500
A max
All Digital Inputs 0 V or VDD
AC PERFORMANCE CHARACTERISTICS5
V
DD = +5 V
V
DD = +15 V
Parameter
Version1
T
A = +25°CTMIN, TMAX
T
A= +25°CTMIN, TMAX
Units
Test Conditions/Comments
DC SUPPLY REJECTION (
GAIN/V
DD)
All
0.02
0.04
0.01
0.02
% per % max
V
DD =
± 5%
CURRENT SETTLING TIME
2
All
350
400
180
200
ns max
To 1/2 LSB. OUT A/OUT B Load = 100
.
WR = CS = 0 V. DB0–DB7 = 0 V to VDD or
VDD to 0 V
PROPAGATION DELAY (From Digital In-
VREF A = VREF B = +10 V
put to 90% of Final Analog Output Current)
All
220
270
80
100
ns max
OUT A, OUT B Load = 100
C
EXT = 13 pF
WR = CS = 0 V DB0–DB7 = 0 V to VDD or
VDD to 0 V
DIGITAL-TO-ANALOG GLITCH IMPULSE
All
160
440
nV sec typ
For Code Transition 00000000 to 11111111
OUTPUT CAPACITANCE
COUTA
All
50
pF max
DAC Latches Loaded with 00000000
COUTB
50
505050pF max
COUTA
120
pF max
DAC Latches Loaded with 11111111
COUTB
120
pF max
AC FEEDTHROUGH
6
VREF A to OUT A
All
–70
–65
–70
–65
dB max
VREF A, VREF B = 20 V p-p Sine Wave
VREF B to OUT B
–70
–65
–70
–65
dB max
@ 100 kHz
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
Output Amplifiers)
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