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參數(shù)資料
| 型號(hào)： | AD7537JN |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT LC2MOS DUAL 24-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時(shí)間： | 250µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 24mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 667k |
AD7537
REV.
–5–
UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary opera-
tion. With an ac input, the circuit performs 2-quadrant multipli-
cation. The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is
loaded with all 0s and amplifier offset adjusted so that VOUTA or
VOUTB is 0 V. Full-scale trimming is accomplished by loading
the DAC register with all 1s and adjusting R1 (R3) so that
VOUTA (VOUTB) = –VIN (4095/4096). For high temperature op-
eration, resistors and potentiometers should have a low Tem-
perature Coefficient. In many applications, because of the
excellent Gain T.C. and Gain Error specifications of the
AD7537, Gain Error trimming is not necessary. In fixed refer-
ence applications, full scale can also be adjusted by omitting R1,
R2, R3, R4 and trimming the reference voltage magnitude.
Figure 4. AD7537 Unipolar Binary Operation
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
Binary Number in
DAC Register
Analog Output,
MSB
LSB
VOUTA or VOUTB
1111 1111 1111
V
IN
4095
4096
1000 0000 0000
V
IN
2048
4096
= 1
2 V IN
0000 0000 0001
V
IN
1
4096
0000 0000 0000
0 V
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is
shown in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that VOUTA (VOUTB) = 0 V. Alternatively, R1,
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10)
varied for VOUTA (VOUTB) = 0 V. Full-scale trimming can be ac-
complished by adjusting the amplitude of VIN or by varying the
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating
over a wide temperature range, it is important that the resistors
be of the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
Figure 5. Bipolar Operation (Offset Binary Coding)
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
Binary Number in
DAC Register
Analog Output,
MSB
LSB
VOUTA or VOUTB
1111 1111 1111
+V
IN
2047
2048
1000 0000 0001
+V
IN
1
2048
1000 0000 0000
0 V
0111 1111 1111
V
IN
1
2048
0000 0000 0000
V
IN
2048
=V
IN
Applications–
A
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| AD7537JNZ | 功能描述:IC DAC 12BIT LC2MOS DUAL 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
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