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參數(shù)資料
| 型號(hào)： | AD7537KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL MULT 24DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 設(shè)置時(shí)間： | 250µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 24mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 667k |
AD7537
REV.
–4–
PIN FUNCTION DESCRIPTION
PIN
MNEMONIC
DESCRIPTION
1
AGNDA
Analog Ground for DAC A.
2IOUTA
Current output terminal of DAC A.
3RFBA
Feedback resistor for DAC A.
4VREFA
Reference input to DAC A.
5
CS
Chip Select Input Active low.
6–14
DB0–DB7
Eight data inputs, DB0–DB7.
12
DGND
Digital Ground.
15
A0
Address Line 0.
16
A1
Address Line 1.
17
CLR
Clear Input. Active low. Clears all
registers.
18
WR
Write Input. Active low.
19
UPD
Updates DAC Registers from inputs
registers.
20
VDD
Power supply input. Nominally +12 V
to +15 V, with
±10% tolerance.
21
VREFB
Reference input to DAC B.
22
RFBB
Feedback resistor for DAC B.
23
IOUTB
Current output terminal of DAC B.
24
AGNDB
Analog Ground for DAC B.
PLCC
PIN CONFIGURATIONS
CIRCUIT INFORMATION – D/A SECTION
The AD7537 contains two identical 12-bit multiplying D/A
converters. Each DAC consists of a highly stable R-2R ladder
and 12 N-channel current steering switches. Figure 2 shows a
simplified D/A circuit for DAC A. In the R-2R ladder, binary
weighted currents are steered between IOUTA and AGNDA. The
current flowing in each ladder leg is constant, irrespective of
switch state. The feedback resistor RFBA is used with an op amp
(see Figures 4 and 5) to convert the current flowing in IOUTA to
a voltage output.
Figure 2. Simplified Circuit Diagram for DAC A
EQUIVALENT CIRCUIT ANALYSIS
Figure 3 shows the equivalent circuit for one of the D/A con-
verters (DAC A) in the AD7537. A similar equivalent circuit
can be drawn for DAC B.
COUT is the output capacitance due to the N-channel switches
and varies from about 50 pF to 150 pF with digital input code.
The current source ILKG is composed of surface and junction
leakages and approximately doubles every 10
°C. R0 is the
equivalent output resistance of the device which varies with
input code.
DIGITAL CIRCUIT INFORMATION
The digital inputs are designed to be both TTL and 5 V CMOS
compatible. All logic inputs are static protected MOS gates with
typical input currents of less than 1 nA.
Table I. AD7537 Truth Table
CLR UPD CS WR A1 A0 FUNCTION
1
X
X X
No Data Transfer
1
X
1
X X
No Data Transfer
0
X
X X
All Registers Cleared
1
0
DAC A LS Input Register
Loaded with DB7–DB0 (LSB)
1
0
1
DAC A MS Input Register
Loaded with DB3 (MSB)–DB0
1
0
1
0
DAC B LS Input Register
Loaded with DB7–DB0 (LSB)
1
0
1
DAC B MS Input Register
Loaded with DB3 (MSB)–DB0
1
0
1
0
X X
DAC A, DAC B Registers
Updated Simultaneously from
Input Registers
1
0
X X
DAC A, DAC B Registers are
Transparent
NOTES: X = Don’t care
Figure 3. Equivalent Analog Circuit for DAC A
A
PDIP and SOIC
(PDIP)
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