AD7538
Rev. B | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREF 1
RFB 2
IOUT 3
AGND 4
VSS
24
VDD
23
WR
22
CS
21
DGND 5
(MSB) DB13 6
DB12 7
LDAC
20
DB0 (LSB)
19
DB1
18
DB11 8
DB2
17
DB10 9
DB3
16
DB9 10
DB4
15
DB8 11
DB5
14
DB7 12
DB6
13
AD7538
TOP VIEW
(Not to Scale)
0
11
3
9
-0
0
3
Figure 3. Pin Configuration
Table 5. Pin Function Description
Pin No.
Mnemonic
Description
1
VREF
Voltage Reference.
2
RFB
Feedback Resistor. Used to close the loop around an external op amp.
3
IOUT
Current Output Terminal.
4
AGND
Analog Ground
5
DGND
Digital Ground.
6 to 19
DB13 to DB0
Data Inputs. Bit DB13 (MSB) to Bit DB0 (LSB).
20
LDAC
Chip Select Input. Active low.
21
CS
Asynchronous Load DAC Input. Active low.
22
WR
Write Input. Active low.
CS
LDAC
WR
Operation
0
1
0
Load input register.
1
0
Load DAC register from input register.
0
Input and DAC registers are transparent.
1
No operation.
1
No operation.
23
VDD
+12 V to +15 V Supply Input.
24
VSS
Bias pin for high temperature low leakage configuration. To implement low leakage system, the pin should be
1 X = don’t care.