參數(shù)資料
型號: AD7538KRZ
廠商: Analog Devices Inc
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC DAC 14BIT W/BUFF 24-SOIC
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 31
設置時間: 1.5µs
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1W
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應商設備封裝: 24-SOIC W
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 667k
AD7538
Rev. B | Page 12 of 16
PROGRAMMABLE GAIN AMPLIFIER
The circuit shown in Figure 9 provides a programmable gain
amplifier (PGA). In it the DAC behaves as a programmable
resistance and thus allows the circuit gain to be digitally
controlled.
AD7538
N
IOUT
VDD
VSS
VOUT
VIN
VREF
GND
DIGITAL
INPUT
A
RFB
NOTES
1. RESISTOR RFB IS ACTUALLY
INCLUDED ON THE DICE.
01
13
9-
00
9
Figure 9. Programmable Gain Amplifier (PGA)
The transfer function of Figure 9 is:
FB
EQ
IN
OUT
R
V
Gain
=
(1)
REQ is the equivalent transfer impedance of the DAC from the
VREF pin to the IOUT pin and can be expressed as
N
R
IN
n
EQ
2
=
(2)
where:
n
is the resolution of the DAC.
N
is the DAC input code in decimal.
RIN
is the constant input impedance of the DAC (RIN = RLAD).
Substituting this expression into Equation 1 and assuming
zero gain error for the DAC (RIN = RFB), the transfer function
simplifies to
N
V
n
IN
OUT
2
=
(3)
The ratio N/2n is commonly represented by the term, D, and, as
such, is the fractional representation of the digital input word.
D
N
V
n
IN
OUT
1
2
=
=
(4)
Equation 4 indicates that the gain of the circuit can be varied
from 16,384 down to unity (actually 16,384/16,383) in 16,383
steps. The all 0s code is never applied. This avoids an open-loop
condition thereby saturating the amplifier. With the all 0s code
excluded there remains (2n – 1) possible input codes allowing a
choice of (2n – 1) output levels. In decibels the dynamic range is
(
)
dB
84
1
2
log
20
log
20
10
=
=
n
IN
OUT
V
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