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參數(shù)資料
| 型號： | AD7545ALPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT W/BUFF MULT 20PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 2µs |
| 位數(shù)： | 12 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | * |
–2–
REV. A
AD7545–SPECIFICATIONS
VDD = +5 V
VDD = +15 V
Limits
Parameter
Version
TA = + 25 CTMIN, TMAX
1
TA = + 25 CTMIN, TMAX
1
Units
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
All
12
Bits
J, A, S
±2
LSB max
K, B, T
±1
LSB max
L, C, U
±1/2
LSB max
GL, GC, GU
±1/2
LSB max
Differential Nonlinearity
J, A, S
±4
LSB max
10-Bit Monotonic TMIN to TMAX
K, B, T
±1
LSB max
12-Bit Monotonic TMIN to TMAX
L, C, U
±1
LSB max
12-Bit Monotonic TMIN to TMAX
GL, GC, GU
±1
LSB max
12-Bit Monotonic TMIN to TMAX
Gain Error (Using Internal RFB)
2
J, A, S
±20
±25
LSB max
DAC Register Loaded with
K, B, T
±10
±15
LSB max
1111 1111 1111
L, C, U
±5
±6
±10
LSB max
Gain Error Is Adjustable Using
GL, GC, GU
±1
±2
±6
±7
LSB max
the Circuits of Figures 4, 5, and 6
Gain Temperature Coefficient
3
Gain/Temperature
All
±5
±10
ppm/
°C max
Typical Value is 2 ppm/
°C for V
DD = +5 V
DC Supply Rejection
3
Gain/V
DD
All
0.015
0.03
0.01
0.02
% per % max
V
DD =
±5%
Output Leakage Current at OUT1
J, K, L, GL
10
50
10
50
nA max
DB0–DB11 = 0 V; WR, CS = 0 V
A, B, C, GC
10
50
10
50
nA max
S, T, U, GU
10
200
10
200
nA max
DYNAMIC PERFORMANCE
Current Settling Time
3
All
2
s max
To 1/2 LSB. OUT1 Load = 100
. DAC
Output Measured from Falling Edge of
WR, CS = 0.
Propagation Delay
3 (from Digital
Input Change to 90%
of Final Analog Output)
All
300
–
250
–
ns max
OUT1 Load = 100
, C
EXT = 13 pF
4
Digital-to-Analog Glitch Inpulse
All
400
–
250
–
nV sec typ
VREF = AGND
AC Feedthrough
5
At OUT1
All
5
mV p-p typ
VREF =
±10 V, 10 kHz Sinewave
REFERENCE INPUT
Input Resistance
All
7
k
min
Input Resistance TC = –300 ppm/
°C typ
(Pin 19 to GND)
25
k
max
Typical Input Resistance = 11 k
ANALOG OUTPUT
Output Capacitance
3
COUT1
All
70
pF max
DB0–DB11 = 0 V, WR, CS = 0 V
COUT1
200
pF max
DB0–DB11 = VDD, WR, CS = 0 V
DIGITAL INPUTS
Input High Voltage
VIH
All
2.4
13.5
V min
Input Low Voltage
VIL
All
0.8
1.5
V max
Input Current
6
IIN
All
±1
±10
±1
±10
A max
VIN = 0 or VDD
Input Capacitance
3
DB0–DB11
All
5
pF max
VIN = 0
WR, CS
All
20
pF max
VIN = 0
SWITCHING CHARACTERISTICS7
Chip Select to Write Setup Time
All
280
380
180
200
ns min
See Timing Diagram
tCS
200
270
120
150
ns typ
Chip Select to Write Hold Time
tCH
All
0
ns min
Write Pulse Width
tWR
All
250
400
160
240
ns min
tCS
≥ t
WR, tCH
≥ 0
175
280
100
170
ns typ
Data Setup Time
All
140
210
90
120
ns min
tDS
100
150
60
80
ns typ
Data Hold Time
tDH
All
10
ns min
POWER SUPPLY
IDD
All
2
mA max
All Digital Inputs VIL or VIH
100
500
100
500
A max
All Digital Inputs 0 V to VDD
10
A typ
All Digital Inputs 0 V to VDD
NOTES
1Temperature range as follows: J, K, L, GL versions, 0
°C to +70°C; A, B, C, GC versions, –25°C to +85°C; S, T, U GU versions, –55°C to +125°C.
2This includes the effect of 5 ppm max gain TC.
3Guaranteed but not tested.
4DB0–DB11 = 0 V to V
DD or VDD to 0 V.
5Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND.
6Logic inputs are MOS gates. Typical input current (+25
°C) is less than 1 nA.
7Sample tested at +25
°C to ensure compliance.
Specifications subject to change without notice.
(VREF = +10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)
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