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參數(shù)資料
| 型號： | AD7545JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULTIPLYING 20-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 設(shè)置時間： | 2µs |
| 位數(shù)： | 12 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
AD7545
–3–
REV. A
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25
°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +17 V
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V
VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . .
±25 V
VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Power Dissipation (Any Package) to +75
°C . . . . . . . 450 mW
Derates above +75
°C . . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature
TERMINOLOGY
RELATIVE ACCURACY
The amount by which the D/A converter transfer function
differs from the ideal transfer function after the zero and full-
scale points have been adjusted. This is an endpoint linearity
measurement.
DIFFERENTIAL NONLINEARITY
The difference between the measured change and the ideal
change between any two adjacent codes. If a device has a differ-
ential nonlinearity of less than 1 LSB it will be monotonic, i.e.,
the output will always increase for an increase in digital code
applied to the D/A converter.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is mea-
sured from the time a digital input changes to the point at which
the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is a measure of the amount of charge injected from the
digital inputs to the analog outputs when the inputs change
state. It is usually specified as the area of the glitch in nV secs
and is measured with VREF = AGND and an ADLH0032CG as
the output op amp, C1 (phase compensation) = 33 pF.
Commercial (J, K, L, GL) Grades . . . . . . . . 0
°C to +70°C
Industrial (A, B, C, GC) Grades . . . . . . . . –25
°C to +85°C
Extended (S, T, U, GU) Grades . . . . . . . –55
°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65
°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7545 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
1
Maximum
Gain Error
Temperature
Relative
TA = +25 C
Package
Model2
Range
Accuracy
VDD = +5 V
Options3
AD7545JN
0
°C to +70°C
± 2 LSB
±20 LSB
N-20
AD7545AQ
–25
°C to +85°C
± 2 LSB
±20 LSB
Q-20
AD7545SQ
–55
°C to +125°C ± 2 LSB
±20 LSB
Q-20
AD7545KN
0
°C to +70°C
± 1 LSB
±10 LSB
N-20
AD7545BQ
–25
°C to +85°C
± 1 LSB
±10 LSB
Q-20
AD7545TQ
–55
°C to +125°C ± 1 LSB
±10 LSB
Q-20
AD7545LN
0
°C to +70°C
± 1/2 LSB
±5 LSB
N-20
AD7545CQ
–25
°C to +85°C
± 1/2 LSB
±5 LSB
Q-20
AD7545UQ
–55
°C to +125°C ± 1/2 LSB
±5 LSB
Q-20
AD7545GLN
0
°C to +70°C
± 1/2 LSB
±1 LSB
N-20
AD7545GCQ
–25
°C to +85°C
± 1/2 LSB
±1 LSB
Q-20
AD7545GUQ
–55
°C to +125°C ± 1/2 LSB
±1 LSB
Q-20
AD7545JP
0
°C to +70°C
± 2 LSB
±20 LSB
P-20A
AD7545SE
–55
°C to +125°C ± 2 LSB
±20 LSB
E-20A
AD7545KP
0
°C to +70°C
± 1 LSB
±10 LSB
P-20A
AD7545TE
–55
°C to +125°C ± 1 LSB
±10 LSB
E-20A
AD7545LP
0
°C to +70°C
± 1/2 LSB
±5 LSB
P-20A
AD7545UE
–55
°C to +125°C ± 1/2 LSB
±5 LSB
E-20A
AD7545GLP
0
°C to +70°C
± 1/2 LSB
±1 LSB
P-20A
AD7545GUE
–55
°C to +125°C ± 1/2 LSB
±1 LSB
E-20A
NOTES
1Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip
packages (Q-20).
2To order MIL-STD-883, Class B process parts, add /883B to part number.
Contact local sales office for military data sheet. For U.S. Standard Military
DRAWING (SMD) see DESC drawing 5962-87702.
3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip.
Write Cycle Timing Diagram
CHIP
SELECT
WRITE
DATA IN
(DB0–DB11)
VDD
0
VDD
0
VDD
0
DATA VALID
VIH
VIL
tDS
tDH
tWR
tCS
tCH
MODE SELECTION
CS AND WR LOW, DAC RESPONDS
TO DATA BUS (DB0–DB11) INPUTS.
WRITE MODE:
HOLD MODE:
EITHER CS OR WR HIGH, DATA BUS
(DB0–DB11) IS LOCKED OUT; DAC
HOLDS LAST DATA PRESENT WHEN
WR OR CS ASSUMED HIGH STATE.
NOTES:
VDD = +5V; tr = tf = 20ns
VDD = +15V; tr = tf = 40ns
ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO
90% OF VDD.
TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL/2.
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