參數(shù)資料
型號： AD7564AR-B
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： LC2MOS +3.3 V/+5 V, Low Power, Quad 12-Bit DAC
中文描述： QUAD, SERIAL INPUT LOADING, 3.5 us SETTLING TIME, 12-BIT DAC, PDSO28
封裝： SOIC-28
文件頁數(shù)： 12/16頁
文件大?。?/td> 392K
代理商： AD7564AR-B
REV. A
AD7564
–12–
In the current mode circuit of Figure 19, I
OUT2
and hence I
OUT1
,
is biased positive by an amount V
BIAS
. For the circuit to operate
correctly, the DAC ladder termination resistor must be con-
nected internally to I
OUT2
. This is the case with the AD7564.
The output voltage is given by:
V
OUT
=
D
×
R
FB
R
DAC
×
(
V
BIAS
–
V
IN
)
+
V
BIAS
As D varies from 0 to 4095/4096, the output voltage varies
from V
OUT
= V
BIAS
to V
OUT
= 2 V
BIAS
– V
IN
. V
BIAS
should be a
low impedance source capable of sinking and sourcing all pos-
sible variations in current at the I
OUT2
terminal without any
problems.
Voltage Mode Circuit
Figure 20 shows DAC A of the AD7564 operating in the
voltage-switching mode. The reference voltage, V
IN
is applied
to the I
OUT1
pin, I
OUT2
is connected to AGND and the output
voltage is available at the V
REF
terminal. In this configuration, a
positive reference voltage results in a positive output voltage;
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder re-
sistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt-
age input should be driven from a low impedance source.
It is important to note that V
IN
is limited to low voltages be-
cause the switches in the DAC no longer have the same source-
drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, V
IN
must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.
A1
V
REF
A
R
FB
A
I
OUT1
A
V
IN
V
OUT
I
OUT2
A
R1
R2
AD7564
DAC A
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
NOTES
Figure 20. Single Supply Voltage Switching Mode
Operation
BIPOLAR OPERATION
4-Quadrant Multiplication)
Figure 18 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7564. The coding
is offset binary as shown in Table IV. When V
IN
is an ac signal,
the circuit performs 4-quadrant multiplication. To maintain
the gain error specifications, resistors R3, R4 and R5 should be
ratio matched to 0.01%.
A1
DAC A
AD7564
V
REF
A
V
IN
NOTES:
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
R2 10
R1 20
SIGNAL
GND
C1
R
FB
A
I
OUT1
A
V
OUT
R4 20k
I
OUT2
A
20k
R5
R4 20
A2
R3
10k
Figure 18. Bipolar Operation (4-Quadrant Multiplication)
Table IV. Bipolar (Offset Binary) Code Table
Digital Input
MSB . . . LSB
Analog Output
(V
OUT
as Shown in Figure 18)
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
–V
REF
(2047/2048)
–V
REF
(1/2048)
–V
REF
(0/2048 = 0)
–V
REF
(1/2048)
–V
REF
(2047/2048)
–V
REF
(2048/2048) = –V
REF
NOTE
Nominal LSB size for the circuit of Figure 18 is given by: V
REF
(1/2048).
SINGLE SUPPLY APPLICATIONS
The “–B” versions of the AD7564 are specified and tested for
single supply applications. Figure 19 shows a typical circuit for
operation with a single +3.3 V to +5 V supply.
A1
DAC A
AD7564
V
REF
A
R
FB
A
I
OUT1
A
I
OUT2
A
V
IN
V
BIAS
V
OUT
NOTES:
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 19. Single Supply Current Mode Operation
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