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參數(shù)資料
| 型號(hào)： | AD7564ARZ-B |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD 3.3V LP 28SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 設(shè)置時(shí)間： | 500ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 8 電流，單極；8 電流，雙極 |
| 采樣率（每秒）： | 1.8M |
REV.
AD7564
–12–
In the current mode circuit of Figure 19, IOUT2 and hence IOUT1,
is biased positive by an amount VBIAS. For the circuit to operate
correctly, the DAC ladder termination resistor must be con-
nected internally to IOUT2. This is the case with the AD7564.
The output voltage is given by:
VOUT = D ×
RFB
RDAC
× (V
BIAS – V IN )
+V
BIAS
As D varies from 0 to 4095/4096, the output voltage varies
from VOUT = VBIAS to VOUT = 2 VBIAS – VIN. VBIAS should be a
low impedance source capable of sinking and sourcing all pos-
sible variations in current at the IOUT2 terminal without any
problems.
Voltage Mode Circuit
Figure 20 shows DAC A of the AD7564 operating in the
voltage-switching mode. The reference voltage, VIN is applied
to the IOUT1 pin, IOUT2 is connected to AGND and the output
voltage is available at the VREF terminal. In this configuration, a
positive reference voltage results in a positive output voltage;
making single supply operation possible. The output from the
DAC is a voltage at a constant impedance (the DAC ladder re-
sistance). Thus, an op amp is necessary to buffer the output
voltage. The reference voltage input no longer sees a constant
input impedance, but one which varies with code. So, the volt-
age input should be driven from a low impedance source.
It is important to note that VIN is limited to low voltages be-
cause the switches in the DAC no longer have the same source-
drain voltage. As a result, their on-resistance differs and this
degrades the integral linearity of the DAC. Also, VIN must not
go negative by more than 0.3 volts or an internal diode will turn
on, causing possible damage to the device. This means that the
full-range multiplying capability of the DAC is lost.
A1
VREFA
RFBA
IOUT1A
VIN
VOUT
IOUT2A
R1
R2
AD7564
DAC A
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER.
NOTES
Figure 20. Single Supply Voltage Switching Mode
Operation
BIPOLAR OPERATION
4-Quadrant Multiplication)
Figure 18 shows the standard connection diagram for bipolar
operation of any one of the DACs in the AD7564. The coding
is offset binary as shown in Table IV. When VIN is an ac signal,
the circuit performs 4-quadrant multiplication. To maintain
the gain error specifications, resistors R3, R4 and R5 should be
ratio matched to 0.01%.
A1
DAC A
AD7564
VREFA
VIN
NOTES:
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
R2 10
R1 20
SIGNAL
GND
C1
RFBA
IOUT1A
VOUT
R4 20k
IOUT2A
20k
R5
R4 20
A2
R3
10k
Figure 18. Bipolar Operation (4-Quadrant Multiplication)
Table IV. Bipolar (Offset Binary) Code Table
Digital Input
Analog Output
MSB . . . LSB
(VOUT as Shown in Figure 18)
1111 1111 1111
–VREF (2047/2048)
1000 0000 0001
–VREF (1/2048)
1000 0000 0000
–VREF (0/2048 = 0)
0111 1111 1111
–VREF (1/2048)
0000 0000 0001
–VREF (2047/2048)
0000 0000 0000
–VREF (2048/2048) = –VREF
NOTE
Nominal LSB size for the circuit of Figure 18 is given by: VREF (1/2048).
SINGLE SUPPLY APPLICATIONS
The “–B” versions of the AD7564 are specified and tested for
single supply applications. Figure 19 shows a typical circuit for
operation with a single +3.3 V to +5 V supply.
A1
DAC A
AD7564
VREFA
RFBA
IOUT1A
IOUT2A
VIN
VBIAS
VOUT
NOTES:
1. ONLY ONE DAC IS SHOWN FOR CLARITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5–15pF) MAY BE
REQUIRED WHEN USING HIGH SPEED AMPLIFIER, A1.
Figure 19. Single Supply Current Mode Operation
B
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