AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = 15 V; V
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閰嶇敤锛� EVAL-AD7612CBZ-ND - BOARD EVALUATION FOR AD7612
Data Sheet
AD7612
Rev. A | Page 5 of 32
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = 15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
t1
10
ns
Time Between Conversions
t2
Warp Mode/Normal Mode/Impulse Mode1
1.33/1.67/2
渭s
CNVST Low to BUSY High Delay
t3
35
ns
BUSY High All Modes (Except Master Serial Read After Convert)
t4
Warp Mode/Normal Mode/Impulse Mode
950/1250/1450
ns
Aperture Delay
t5
2
ns
End of Conversion to BUSY Low Delay
t6
10
ns
Conversion Time
t7
Warp Mode/Normal Mode/Impulse Mode
950/1250/1450
ns
Acquisition Time
t8
Warp Mode/Normal Mode/Impulse Mode
380
ns
RESET Pulse Width
t9
10
ns
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
t10
Warp Mode/Normal Mode/Impulse Mode
910/1160/1410
ns
DATA Valid to BUSY Low Delay
t11
20
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
2
15
ns
MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
t14
10
ns
CS Low to Internal SDCLK Valid Delay2
t15
10
ns
CS Low to SDOUT Delay
t16
10
ns
CNVST Low to SYNC Delay, Read During Convert
t17
Warp Mode/Normal Mode/Impulse Mode
65/315/560
ns
SYNC Asserted to SDCLK First Edge Delay
t18
3
ns
Internal SDCLK Period3
t19
30
45
ns
Internal SDCLK High3
t20
15
ns
Internal SDCLK Low3
t21
10
ns
SDOUT Valid Setup Time3
t22
4
ns
SDOUT Valid Hold Time3
t23
5
ns
SDCLK Last Edge to SYNC Delay3
t24
5
ns
CS High to SYNC HI-Z
t25
10
ns
CS High to Internal SDCLK HI-Z
t26
10
ns
CS High to SDOUT HI-Z
t27
10
ns
BUSY High in Master Serial Read After Convert3
t28
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode
t29
830/1070/1310
ns
SYNC Deasserted to BUSY Low Delay
t30
25
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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