參數(shù)資料
型號： AD7621ASTRL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 16-Bit, 1 LSB INL, 3 MSPS PulSAR ADC
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48
封裝： MO-026-BBC, LQFP-48
文件頁數(shù)： 7/26頁
文件大?。?/td> 265K
代理商： AD7621ASTRL
REV. Pr D
PRELIMINARY TECHNICAL DATA
AD7621
–7–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type
Description
1, 41, 42
2, 44
3, 40
4
AGND
AVDD
NC
BYTESWAP
P
P
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 2.5 V.
No Connect.
Parallel Mode Selection (8-bit/16-bit). When LOW, the LSB is output on D[7:0]
and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and
the MSB is output on D[7:0].
Straight Binary/Binary Two’s
Complement. When OB/
2C
is HIGH, the digital
output is straight binary; when LOW, the MSB is inverted resulting in a two’s
complement output from its internal shift register.
Conversion mode selection. When HIGH and IMPULSE LOW, this input selects
the fastest mode, the maximum throughput is achievable, and a minimum conversion
rate must be applied in order to guarantee full specified accuracy. When LOW, full
accuracy is maintained independent of the minimum conversion rate.
Conversion mode selection. When HIGH and WARP LOW, this input selects a
reduced power mode. In this mode, the power dissipation is approximately
proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when
HIGH, the serial interface is selected and some bits of the data bus are used as a
serial port.
Bit 0 and Bit 1 of the parallel port data output bus. When SER/
PAR
is HIGH, these
outputs are in high impedance.
When SER/
PAR
is LOW, these pins are Bit 2 and Bit 3 of the Parallel
Port Data Output Bus.
When SER/
PAR
is HIGH
,
EXT/
INT
is LOW, and RDC/SDIN is LOW, which is
serial master read after convert, these inputs, part of the serial port, are used to slow
down if desired the internal serial clock which clocks the data output. In other serial
modes, these pins are high impedance outputs.
When SER/
PAR
is LOW, this output is used as Bit 4 of the Parallel Port
Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital
select input for choosing the internal or an external data clock. With EXT/
INT
tied
LOW, the internal clock is selected on SCLK output. With EXT/
INT
set to a logic
HIGH, output data is synchronized to an external clock signal connected to the
SCLK input.
When SER/
PAR
is LOW, this output is used as Bit 5 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
When SER/
PAR
is LOW, this output is used as Bit 6 of the Parallel Port Data
Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the
SCLK signal. It is active in both master and slave mode.
When SER/
PAR
is LOW, this output is used as Bit 7 of the Parallel PortData
Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an
external data input or a read mode selection input depending on the state of
EXT/
INT
.
When EXT/
INT
is HIGH, RDC/SDIN could be used as a data input to daisy chain
the conversion results from two or more ADCs onto a single SDOUT line. The
digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods
after the initiation of the read sequence.
When EXT/
INT
is LOW, RDC/SDIN is used to select the read mode. When
RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is
complete.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply than the supply
DI
5
OB/
2C
DI
6
WARP
DI
7
IMPULSE
DI
8
SER/
PAR
DI
9, 10
D[0:1]
DO
11,12
D[2:3]or
DI/O
DIVSCLK[0:1]
13
D4
DI/O
or EXT/
INT
14
D5
DI/O
or INVSYNC
15
D6
DI/O
or INVSCLK
16
D7
DI/O
or RDC/SDIN
17
18
OGND
OVDD
P
P
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