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參數(shù)資料
| 型號： | AD7625BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 6MSPS SAR 32LFCSP |
| 設(shè)計資源： | High Speed, Precision, Differential AC-Coupled Drive Circuit for AD7625 (CN0080) |
| 特色產(chǎn)品： | AD7625: 16-Bit, 6MSPS PulSAR Differential ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6M |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 190mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
Data Sheet
AD7625
Rev. A | Page 13 of 24
THEORY OF OPERATION
07652-
030
SW+
COMP
SW–
IN+
REF
(4.096V)
GND
LSB
MSB
32,768C 16,384C
4C
2C
C
CONTROL
LOGIC
CNV+, CNV–
IN–
32,768C 16,384C
4C
2C
C
LSB
MSB
GND
D+, D
–
CLK+, CLK–
DCO+, DCO
–
LVDS INTERFACE
DATA TRANSFER
CONVERSION
CONTROL
OUTPUT CODE
SWITCHES
CONTROL
Figure 18. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7625 is a 6 MSPS, high precision, power efficient, 16-bit
ADC that uses SAR based architecture to provide performance
of 93 dB SNR, ±0.45 LSB INL, and ±0.3 LSB DNL.
The AD7625 is capable of converting 6,000,000 samples per
second (6 MSPS). The device typically consumes 135 mW. The
AD7625 offers the added functionality of a high performance
on-chip reference and on-chip reference buffer.
The AD7625 is specified for use with 5 V and 2.5 V supplies
(VDD1, VDD2). The interface from the digital host to the
AD7625 uses 2.5 V logic only. The AD7625 uses an LVDS
interface to transfer data conversions. The CNV+ and CNV
inputs to the part activate the conversion of the analog input.
The CNV+ and CNV pins can be applied using a CMOS or
LVDS source.
The AD7625 is housed in a space-saving, 32-lead, 5 mm ×
5 mm LFCSP.
CONVERTER INFORMATION
The AD7625 is a 6 MSPS ADC that uses SAR based architecture
incorporating a charge redistribution DAC. Figure 18 shows a
simplified schematic of the ADC. The capacitive DAC consists
of two identical arrays of 16 binary weighted capacitors that are
connected to the two comparator inputs.
During the acquisition phase, the terminals of the array tied
to the input of the comparator are connected to GND via SW+
and SW. All independent switches are connected to the analog
inputs. In this way, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN
inputs. A conversion phase is initiated when the acquisition
phase is complete and the CNV± input goes logic high. Note
that the AD7625 can receive a CMOS (CNV+) or LVDS format
(CNV±) signal.
When the conversion phase begins, SW+ and SW are opened
first. The two capacitor arrays are then disconnected from the
inputs and connected to the GND input. Therefore, the differential
voltage between the inputs (IN+ and IN) captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between GND and 4.096 V
(the reference voltage), the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The
control logic toggles these switches, MSB first, to bring the
comparator back into a balanced condition. At the completion
of this process, the control logic generates the ADC output code.
The AD7625 digital interface uses low voltage differential
signaling (LVDS) to enable high data transfer rates.
The AD7625 conversion result is available for reading after tMSB
(time from the conversion start until MSB is available) has
elapsed. The user must apply a burst LVDS CLK± signal to the
AD7625 to transfer data to the digital host.
The CLK± signal outputs the ADC conversion result onto the
data output D±. The bursting of the CLK± signal is illustrated
in Figure 29 and Figure 30 and is characterized as follows: The
differential voltage on CLK± should be held to create logic low
in the time between tCLKL and tMSB.
The AD7625 has two data read modes. For more information
about the echoed-clock and self-clocked interface modes, see
the Digital Interface section.
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| AD7625BCPZRL7 | 功能描述:IC ADC 16BIT 6MSPS SAR 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7626 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 10 MSPS, PulSAR Differential ADC |
| AD7626_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 10 MSPS, PulSAR Differential ADC |
| AD7626_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 10 MSPS, PulSAR Differential ADC |
| AD7626BCPZ | 功能描述:IC ADC 16BIT 10MSPS DIFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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