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| 型號(hào)： | AD7653ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 1MSPS W/REF 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 145mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)偽差分，單極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7653CBZ-ND - BOARD EVALUATION FOR AD7653 |
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AD7653
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50 ) termination should be added
close to the output of the component that drives this line.
POWER DISSIPATION VS. THROUGHPUT
Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see F
). This power savings depends on the
mode used. In Impulse mode, the AD7653 automatically
reduces power consumption at the end of each conversion
phase. This makes the part ideal for very low power battery
applications. The digital interface and the reference remain
active even during the acquisition phase. To reduce operating
digital supply currents even further, digital inputs need to be
driven close to the power supply rails (i.e., DVDD or DGND),
and OVDD should not exceed DVDD by more than 0.3 V.
Figure 25. Power Dissipation vs. Sampling Rate
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7
t8
ACQUIRE
CONVERT
ACQUIRE
CONVERT
02966-0-011
CNVST
SAMPLE RATE (SPS)
10
02966-0-041
1000000
100
10000
100000
1000
10000
100
1000
1000000
10
WARP MODE POWER
IMPULSE MODE POWER
100000
POW
E
R
D
ISSIPA
TION
(
W)
PDREF = PDBUF = HIGH
CONVERSION CONTROL
Figure 26. Basic Conversion Timing
t9
t8
RESET
DATA
BUSY
02966-0-011
CNVST
shows the detailed timing diagrams of the conversion
process. The AD7653 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD.
Figure 27. RESET Timing
t1
t3
t4
t11
BUSY
DATA
BUS
CS = RD = 0
t10
PREVIOUS CONVERSION DATA
NEW DATA
02966-0-012
CNVST
In Impulse mode, conversions can be automatically initiated. If
CNVST is held LOW when BUSY is LOW, the AD7653 controls
the acquisition phase and automatically initiates a new con-
version. By keeping CNVST LOW, the AD7653 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes low. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7653 can run slightly
faster than the guaranteed 666 kSPS limits in Impulse mode.
This feature does not exist in Warp and Normal modes.
Figure 28. Master Parallel Data Timing for Reading (Continuous Read)
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
Rev. A | Page 19 of 28
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| AD7654 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC |
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