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REV. 0
–20–
AD7654
BUSY
BUSY
AD7654
#2 (UPSTREAM)
AD7654
#1 (DOWNSTREAM)
RDC/SDIN
SDOUT
CNVST
CS
SCLK
RDC/SDIN
SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
Figure 19. Two AD7654s in a Daisy-Chain Configuration
MICROPROCESSOR INTERFACING
The AD7654 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7654 is designed to interface with either a parallel 8-bit
or 16-bit wide interface, a general-purpose serial port, or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7654 to prevent digital noise from coupling into
the ADC. The following section illustrates the use of the AD7654
with an SPI-equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 19 shows an interface diagram between the AD7654 and
an SPI-equipped DSP, ADSP-219x. To accommodate the slower
speed of the DSP, the AD7654 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in response
to an internal timer interrupt. The 32-bit output data are read
with two SPI 16-bit wide access. The reading process could
be initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The Serial Peripheral
Interface (SPI) on the ADSP-219x is configured for master mode
(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, and Clock Phase Bit
(CPHA) = 1 by writing to the SPI Control Register (SPICLTx).
AD7654
*
ADSP-219x
*
SER/
PAR
EXT/
INT
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx or TFSx
BUSY
CS
SDOUT
SCLK
CNVST
RD
INVSCLK
DVDD
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing the AD7654 to SPI Interface
APPLICATION HINTS
Layout
The AD7654 has very good immunity to noise on the power
supplies, as seen in Figure 5. However, care should still be
taken with regard to grounding layout.
The printed circuit board that houses the AD7654 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7654, or, at least as close as possible to the
AD7654. If the AD7654 is in a system where multiple devices
require analog-to-digital ground connections, the connection
should still be made at one point only, a star ground point
that should be established as close as possible to the AD7654.
It is recommended to avoid running digital lines under the
device as these will couple noise onto the die. The analog
ground plane should be allowed to run under the AD7654 to
avoid noise coupling. Fast switching signals like
CNVST
or
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board, and should never run near
analog signal paths. Crossover of digital and analog signals
should be avoided. Traces on different but close layers of the
board should run at right angles to each other. This will reduce
the effect of feedthrough through the board. The power supply
lines to the AD7654 should use as large a trace as possible to
provide low impedance paths and reduce the effect of glitches
on the power supply lines. Good decoupling is also important to
lower the supply’s impedance presented to the AD7654 and
to reduce the magnitude of the supply spikes. Decoupling ceramic
capacitors, typically 100 nF, should be placed on each power
supply’s pins, AVDD, DVDD, and OVDD, close to and ideally
right up against these pins and their corresponding ground pins.
Additionally, low ESR 10
μ
F capacitors should be located in the
vicinity of the ADC to further reduce low frequency ripple.
The DVDD supply of the AD7654 can be either a separate
supply or come from the analog supply, AVDD, or from the
digital interface supply, OVDD. When the system digital supply
is noisy or fast switching digital signals are present, it is recom-
mended that if no separate supply is available, the DVDD digital
supply should be connected to the analog supply AVDD through an
RC filter, as shown in Figure 5, and the system supply should
be connected to the interface digital supply OVDD and the
remaining digital circuitry. When DVDD is powered from the
system supply, it is useful to insert a bead to further reduce high
frequency spikes.
The AD7654 has four different ground pins: REFGND, AGND,
DGND, and OGND. REFGND senses the reference voltage
and should be a low impedance return to the reference because
it carries pulsed currents. AGND is the ground to which most
internal ADC analog signals are referenced. This ground must
be connected with the least resistance to the analog ground
plane. DGND must be tied to the analog or digital ground
plane depending on the configuration. OGND is connected to
the digital system ground.
The layout of the decoupling of the reference voltage is impor-
tant. The decoupling capacitor should be close to the ADC and
connected with short and large traces to minimize parasitic
inductances.
Evaluating the AD7654’s Performance
A recommended layout for the AD7654 is outlined in the
documentation of the evaluation board for the AD7654. The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the Eval-Control BRD2.