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參數(shù)資料
| 型號： | AD7665ACPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT CMOS 5V 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 570k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 74mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極 |
| 配用： | EVAL-AD7665CBZ-ND - BOARD EVALUATION FOR AD7665 |
REV.
–3–
AD7665
Parameter
Conditions
Min
Typ
Max
Unit
POWER SUPPLIES (Continued)
Power Dissipation
6, 7
444 kSPS Throughput
8
64
74
mW
100 SPS Throughput
8
15
W
570 kSPS Throughput
5
93
107
mW
In Power-Down Mode
9
7W
TEMPERATURE RANGE
10
Specified Performance
TMIN to TMAX
–40
+85
°C
NOTES
1LSB means least significant bit. With the ±5 V input range, one LSB is 152.588 V.
2See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4The max should be the minimum of 5.25 V and DVDD + 0.3 V.
5In Warp Mode.
6Tested in Parallel Reading Mode.
7Tested with the 0 V to 5 V range and V
IN – VINGND = 0 V. See Power Dissipation section.
8In Impulse Mode.
9With OVDD below DVDD + 0.3 V and all digital inputs forced to DVDD or DGND, respectively.
10Contact factory for extended temperature range.
Specifications subject to change without notice.
Table I. Analog Input Configuration
Input Voltage
Input
Range
IND(4R)
INC(4R)
INB(2R)
INA(R)
Impedance
1
±4 REF
2
VIN
INGND
REF
5.85 k
W
±2 REF
VIN
INGND
REF
3.41 k
W
±REF
VIN
REF
2.56 k
W
0 V to 4 REF
VIN
INGND
3.41 k
W
0 V to 2 REF
VIN
INGND
2.56 k
W
0 V to REF
VIN
Note 3
NOTES
1Typical analog input impedance.
2With REF = 3 V, in this range, the input should be limited to –11 V to +12 V.
3For this range the input is high impedance.
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
t1
5ns
Time between Conversions
t2
1.75/2/2.25
Note 1
s
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
t3
30
ns
BUSY HIGH All Modes Except in Master Serial Read after
t4
0.75/1/1.25
s
Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t5
2ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)
t7
0.75/1/1.25
s
Acquisition Time
t8
1s
RESET Pulsewidth
t9
10
ns
Refer to Figures 13, 14, 15, and 16 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
0.75/1/1.25
s
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
t11
20
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
C
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