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參數資料
| 型號： | AD7665ASTRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 570 kSPS CMOS ADC |
| 中文描述： | 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | LOW PROFILE, MS-026BBC, QFP-48 |
| 文件頁數： | 7/24頁 |
| 文件大?。?/td> | 348K |
| 代理商： | AD7665ASTRL |
REV. 0
AD7665
–7–
Pin
No.
Mnemonic
Type
Description
21
DATA[8]
or SDOUT
DO
When SER/
PAR
is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7665
provides the conversion result, MSB first, from its internal shift register. The DATA format is
determined by the logic level of OB/
2C
. In serial mode, when EXT/
INT
is LOW, SDOUT is
valid on both edges of SCLK.
In serial mode, when EXT/
INT
is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next
rising edge.
When SER/
PAR
is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT
pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER
/PAR
is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT
= Logic LOW). When a read
sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH
while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High,
SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/
PAR
is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH and EXT/
INT
is HIGH, this output, part of the serial port, is used as
an incomplete read error flag. In slave mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/
PAR
is HIGH, these out-
puts are in high impedance.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data ready clock signal.
Must Be Tied to Digital Ground.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus
is enabled.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
CS
is also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7665. Current conversion, if any, is aborted. If
not used, this pin could be tied to DGND.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions
are inhibited after the current one is completed.
Start Conversion. A falling edge on
CNVST
puts the internal sample/hold into the hold state
and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if
CNVST
is held low when the acquisition phase
(
t
8
) is complete, the internal sample/hold is put into
the hold state and a conversion is immediately started.
Must Be Tied to Analog Ground.
Reference Input Voltage.
Reference Input Analog Ground.
Analog Input Ground.
Analog Inputs. Refer to Table I for input range configuration.
22
DATA[9]
or SCLK
DI/O
23
DATA[10]
or SYNC
DO
24
DATA[11]
or RDERROR
DO
25–28
DATA[12:15]
DO
29
BUSY
DO
30
31
DGND
RD
P
DI
32
CS
DI
33
RESET
DI
34
PD
DI
35
CNVST
DI
36
37
38
39
40, 41,
42, 43
AGND
REF
REFGND
INGND
INA, INB,
INC, IND
P
AI
AI
AI
AI
NOTES
AI = Analog Input.
DI = Digital Input.
DI/O = Bidirectional Digital.
DO = Digital Output.
P = Power.
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