參數(shù)資料
型號: AD7667ACPZ
廠商: Analog Devices Inc
文件頁數(shù): 24/28頁
文件大?。?/td> 0K
描述: IC ADC 16BIT UNIPOLAR 48LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 145mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
輸入數(shù)目和類型: 2 個偽差分,單極
配用: EVAL-AD7667CBZ-ND - BOARD EVALUATION FOR AD7667
AD7667
Rev. 0 | Page 5 of 28
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
Convert Pulse Width
t1
10
ns
Time between Conversions (Warp Mode/Normal Mode/Impulse Mode)1
t2
1/1.25/1.5
s
CNVST LOW to BUSY HIGH Delay
t3
35
ns
BUSY HIGH All Modes except Master Serial Read after Convert
t4
0.75/1/1.25
s
Aperture Delay
t5
2
ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time
t7
0.75/1/1.25
s
Acquisition Time
t8
250
ns
RESET Pulse Width
t9
10
ns
Refer to Figure 35, Figure 36, and Figure 37 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
0.75/1/1.25
s
DATA Valid to BUSY LOW Delay
t11
12
ns
Bus Access Request to DATA Valid
t12
45
ns
Bus Relinquish Time
t13
5
15
ns
Refer to Figure 39 and Figure 40 (Master Serial Interface Modes)2
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay2
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay
t17
25/275/525
ns
SYNC Asserted to SCLK First Edge Delay
t18
3
ns
Internal SCLK Period3
t19
25
40
ns
Internal SCLK HIGH3
t20
12
ns
Internal SCLK LOW3
t21
7
ns
SDOUT Valid Setup Time3
t22
4
ns
SDOUT Valid Hold Time3
t23
2
ns
SCLK Last Edge to SYNC Delay3
t24
3
ns
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read after Convert3
t28
CNVST LOW to SYNC Asserted Delay
t29
0.75/1/1.25
s
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figure 41 and Figure 42 (Slave Serial Interface Modes)2
External SCLK Setup Time
t31
5
ns
External SCLK Active Edge to SDOUT Delay
t32
3
18
ns
SDIN Setup Time
t33
5
ns
SDIN Hold Time
t34
5
ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
1In Warp mode only, the time between conversions is 1ms; otherwise there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
3In Serial Master Read During Convert mode. See Table 4 for Serial Master Read After Convert Mode.
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