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參數(shù)資料
| 型號(hào)： | AD766JNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT W/VREF 16-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 25 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 1.5µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 16-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 16-PDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，雙極；2 電壓，雙極 |
| 采樣率（每秒）： | 390k |
| 產(chǎn)品目錄頁(yè)面： | 781 (CN2011-ZH PDF) |
–7–
REV. A
Applications–AD766
Figure 10. Typical THD vs. Frequency
Figure 11. THD vs. Temperature
INTERFACING THE AD766 TO DIGITAL SIGNAL
PROCESSORS
The AD766 is specifically designed to easily interface to several
popular digital signal processors (DSP) without any additional
logic. Such an interface reduces the possibility of interface prob-
lems and improves system reliability by minimizing component
count.
AD766 TO ADSP-2101
The ADSP-2101 incorporates two complete serial ports which
can be directly interfaced to the AD766 as shown in Figure 12.
The SCLK, TFS and DT outputs of the ADSP-2101 are con-
nected directly to the CLK, LE and DATA inputs of the
AD766, respectively. SCLK is internally generated and can be
programmed to operate from 94 Hz to 6.25 MHz. Data (DT) is
valid on the falling edge of SCLK. After 16 bits have been trans-
mitted, the falling edge of TFS updates the AD766’s data latch.
Using both serial ports of the ADSP-2101, two AD766’s can be
directly interfaced with no additional hardware.
AD766 TO TMS320C25
Figure 13 shows the zero-chip interface to the TMS320C25.
The interface to other TMS320C2X processors is similar. Note
that the C25 should be run in continuous mode. The C25’s
frame synch signal (FSX) will be asserted at the beginning of
each 16-bit word but will actually latch in the previous word.
Figure 12. AD766 to ADSP-2101/ADSP-2102/ ADSP-2105/
ADSP-2111
Figure 13. AD766 to TMS320C25
The CLKS, FSX and DX outputs of the TMS320C25 are con-
nected to the CLK, LE and DATA inputs of the AD766, re-
spectively. Data (DX) is valid on the falling edge of CLKX. The
maximum serial clock rate of the TMS320C25 is 5 MHz.
AD766 TO DSP56000/56001
Figure 14 shows the zero-chip interface to the DSP56000/
56001. The SSI of the 56000/56001 allows serial clock rates up
to fosc/4. SCK, SC2 and STD can be directly connected to the
CLK
, LE and DATA inputs of the AD766. The CRA control
register of the 56000 allows SCK to be internally generated and
software configurable to various divisions of the master clock
frequency. The data (STD) is valid on the falling edge of SCK.
Figure 14. AD766 to DSP56000/DSP56001
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