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參數(shù)資料
| 型號(hào)： | AD767* |
| 英文描述： | Microprocessor-Compatible 12-Bit D/A Converter |
| 中文描述： | 微處理器兼容的12位D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 289K |
AD767
REV. A
–3–
ABSOLUTE MAXIMUM RATINGS*
V
CC
to Power Ground . . . . . . . . . . . . . . . . . . . . .0 V to +18 V
V
EE
to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 11, 13–24)
to Power Ground . . . . . . . . . . . . . . . . . . . .–1.0 V to +7.0 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . .
±
12 V
Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . .
±
12 V
10 V Span R to Reference Ground . . . . . . . . . . . . . . . . .
±
12 V
20 V Span R to Reference Ground . . . . . . . . . . . . . . . . .
±
24 V
Ref Out, V
OUT
(Pins 6, 9) . . . Indefinite short to power ground
Momentary Short to V
CC
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .1000 mW
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
TIMING SPECIFICATIONS
(All Models, T
A
= 25
°
C, V
CC
= +12 V or +15 V,
V
EE
= –12 V or –15 V)
Symbol
Parameter
Min Typ Max
t
DS
Data Valid to End of
CS
(–25
°
C to +85
°
C)
(–55
°
C to +125
°
C)
Data Hold Tine
(–25
°
C to +85
°
C)
(–55
°
C to +125
°
C)
CS
Pulse Width
(–25
°
C to +85
°
C)
(–55
°
C to +125
°
C)
Output Voltage Settling Time* –
40
60
90
10
10
20
40
60
90
–
–
–
–
–
–
–
–
–
2
–
–
–
–
–
–
–
–
–
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
t
DH
t
CS
t
SETT
*t
SETT
is measured referenced to the leading edge of t
CS
. If t
CS
> t
DS
, then
t
SETT
is measured referenced to the beginning of Data Valid.
PIN CONFIGURATION
PLCC
DIP
ORDERING GUIDE
Linearity
Error Max
T
MIN
–T
MAX
Gain T.C.
Max
ppm/
8
C
Temperature
Range
8
C
Model
1
Package
AD767JN
AD767JP
AD767KN Plastic DIP
AD767KP
AD767AD
AD767BD
AD767SD/
883B
AD767A
Chips
NOTES
1
D = Ceramic DIP; N = Plastic DIP; P = Plastic Leaded Chip Carrier.
2
For details on grade and package offerings screened in accordance with MIL-STD-883, refer to
the Analog Devices Military Products Databook or current AD767/883B data sheet.
Plastic DIP
PLCC
0 to +70
0 to +70
0 to +70
0 to +70
–25 to +85
–25 to +85
±
1 LSB
±
1 LSB
±
1/2 LSB
±
1/2 LSB
±
1 LSB
±
1/2 LSB
30
30
15
15
30
15
PLCC
Ceramic DIP
Ceramic DIP
Ceramic DIP
–55 to +125
Note 2
Note 2
N/A
–25 to +85
±
1 LSB
30
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