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參數(shù)資料
| 型號： | AD7678ACPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT SAR W/BUFF 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 26mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7678CB-ND - BOARD EVALUATION FOR AD7678 |
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AD7678
Rev. A | Page 9 of 28
Pin No.
Mnemonic
Description
13
D6
or EXT/INT
DI/O
In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for
choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is
selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an
external clock signal connected to the SCLK input.
14
D7
or INVSYNC
DI/O
In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the
SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15
D8
or INVSCLK
DI/O
In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is
active in both master and slave modes.
16
D9
or RDC/SDIN
DI/O
In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus.
When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH,
RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the
read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When
RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should
not exceed DVDD by more than 0.3 V.
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground.
21
D10
or SDOUT
DO
In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7678 provides the
conversion result, MSB first, from its internal shift register. The data format is determined by the logic
level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial
mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is
valid on the next rising edge.
22
D11
or SCLK
DI/O
In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus.
When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or
output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
23
D12
or SYNC
DO
In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus.
When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while SDOUT output is valid.
24
D13
or RDERROR
DO
In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus.
In MODE = 3 (serial mode) and when EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started and not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed high.
25–28
D[14:17]
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
interface mode.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
30
DGND
P
Must Be Tied to Digital Ground.
31
RD
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7678. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
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|---|---|
| AD7678AST | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:18-BIT, 100KSPS SAR ADC - Bulk 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LQFP48 |
| AD7678ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 18BIT PARALLEL/SERL 48LQFP - Tape and Reel |
| AD7678ASTZ | 功能描述:IC ADC 18BIT SAR 100KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7678ASTZ | 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LQFP48 |
| AD7678ASTZRL | 功能描述:IC ADC 18BIT SAR 100KSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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