參數(shù)資料
型號(hào): AD7679ACPRL
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
中文描述: 1-CH 18-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48
封裝: MO-220-VKKD-2, LFCSP-48
文件頁數(shù): 15/28頁
文件大?。?/td> 1186K
代理商: AD7679ACPRL
AD7679
CIRCUIT INFORMATION
Rev. 0 | Page 15 of 28
IN+
REF
REFGND
IN–
MSB
4C
2C
C
C
LSB
SW+
SWITCHES
CONTROL
262,144C 131,072C
MSB
4C
2C
C
C
LSB
SW–
BUSY
OUTPUT
CODE
CNVST
CONTROL
LOGIC
COMP
262,144C 131,072C
03085–0–025
Figure 23. ADC Simplified Schematic
The AD7679 is a very fast, low power, single-supply, precise
18-bit analog-to-digital converter (ADC) using successive
approximation architecture.
CONVERTER OPERATION
The AD7679 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary weighted capacitors that are
connected to the two comparator inputs.
The AD7679’s linearity and dynamic range are similar or better
than many Σ-Δ ADCs. With the advantages of its successive
architecture, which ease multiplexing and reduce power with
throughput, it can be advantageous in applications that
normally use Σ-Δ ADCs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW–.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN– inputs. When the
acquisition phase is complete and the CNVST input goes low, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW– are opened first. The two capacitor arrays
are then disconnected from the inputs and connected to the
REFGND input. Therefore, the differential voltage between the
IN+ and IN– inputs captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
by binary weighted voltage steps (V
REF
/2, V
REF
/4...V
REF
/262144).
The control logic toggles these switches, starting with the MSB
first, to bring the comparator back into a balanced condition.
After completing this process, the control logic generates the
ADC output code and brings the BUSY output low.
The AD7679 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
The AD7679 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings
and allows for flexible configurations as either a serial or
parallel interface. The AD7679 is pin-to-pin compatible with
the AD7674, AD7676, and AD7678.
相關(guān)PDF資料
PDF描述
AD7679AST 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
AD7679ASTRL 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
AD7675 16-Bit, 100 kSPS, Differential ADC
AD7675AST 16-Bit, 100 kSPS, Differential ADC
AD7675ASTRL 16-Bit, 100 kSPS, Differential ADC
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AD7679AST 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 18-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7679 LQFP48
AD7679ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 18-bit Parallel/Serial 48-Pin LQFP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 570KSPS 18BIT PARALLEL/SERL 48LQFP - Tape and Reel
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