參數資料
| 型號： | AD767JPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 6/8頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT W/AMP 28-PLCC |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 750 |
| 設置時間： | 3µs |
| 位數： | 12 |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應商設備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
AD767
REV. A
–6–
USING THE AD767 WITH THE AD588 HIGH PRECISION
VOLTAGE REFERENCE
The AD767 is specified for gain drift from 15 ppm/
°C to
30 ppm/
°C (depending on grade) using its internal 10 volt
reference. Since the internal reference contributes the majority
of this drift, an external high-precision voltage reference will
greatly improve performance over temperature. As shown in
Figure 4, the 10 volt output from the AD588 is used as the
reference. With a 1.5 ppm/
°C output voltage drift the AD588
contributes less than 1/2 LSB gain drift when used with the
AD767 over the industrial temperature range. Using this
combination may result in apparent increases in full-scale error
due to the differences between the internal reference by which
the device is laser trimmed and the external reference with
which the device is actually applied. The AD767 internal
reference is specified to be 10 volts
±100 mV whereas the
AD588 is specified as 10 volts
±1 mV. This may result in up to
101 mV of apparent full-scale error beyond the
±25 mV
specified AD767 gain error. The 500
potentiometer in series
with the reference input allows adequate trim range to null this
error.
GROUNDING RULES
The AD767 brings out separate analog and power grounds to
allow optimum connections for low noise and high-speed
performance. These grounds should be tied together at one
point, usually the device power ground. The separate ground
returns are provided to minimize current flow in low-level signal
paths.
The analog ground at Pin 5 is the ground point for the output
amplifier and is thus the “high quality” ground for the AD767;
it should be connected directly to the analog reference point of
the system. The power ground at Pin 12 can be connected to
the most convenient ground point; analog power return is
preferred. If power ground contains high frequency noise
beyond 200 mV, this noise may feed through the converter, thus
some caution will be required in applying these grounds.
It is also important to apply decoupling capacitors properly on
the power supplies for the AD767. The correct method for
decoupling is to connect a capacitor from each power supply pin
of the AD767 to the analog ground pin of the AD767. Any load
driven by the output amplifier should also be referred to the
analog ground pin.
OPTIMIZING SETTLING TIME
The dynamic performance of the AD767’s output amplifier can
be optimized by adding a small (20 pF) capacitor across the
feedback resistor. Figure 5 shows the improvement in both
large-signal and small-signal settling for the 10 V range. In
Figure 5a, the top trace shows the data inputs (DB11–DB0 tied
together), the second trace shows the CS pulse, and the lower
two traces show the analog outputs for CF = 0 and 20 pF
respectively.
Figure 5a. Large Scale Settling
Figures 5b and 5c show the settling time for the transition from
all bits on to all bits off. Note that the settling time to
±1/2 LSB
for the 10 V step is improved from 2.4 microseconds to 1.6
microseconds by the addition of the 20 pF capacitor.
Figure 5b. Fine-Scale Settling, CF = 0 pF
Figure 5c. Fine-Scale Settling, CF = 20 pF
Figures 5d and 5e show the settling time for the transition from
all bits off to all bits on. The improvement in settling time
gained by adding CC = 20 pF is similar.
Figure 5d. Fine-Scale Settling, CF = 0 pF
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