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參數(shù)資料
| 型號： | AD7680BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT LP UNIPOLR 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 26.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
AD7680
Rev. A | Page 12 of 24
CIRCUIT INFORMATION
The AD7680 is a fast, low power, 16-bit, single-supply ADC. The
part can be operated from a 2.5 V to 5.5 V supply and is capable of
throughput rates of 100 kSPS when provided with a 2.5 MHz clock.
The AD7680 provides the user with an on-chip track-and-hold
ADC and a serial interface housed in a tiny 6-lead SOT-23
package or in an 8-lead MSOP package, which offer the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive approximation
ADC. The analog input range for the AD7680 is 0 V to VDD. An
external reference is not required for the ADC nor is there a
reference on-chip. The reference for the AD7680 is derived from
the power supply and thus gives the widest dynamic input range.
The AD7680 also features a power-down option to save power
between conversions. The power-down feature is implemented
across the standard serial interface as described in the Modes of
Operation section.
CONVERTER OPERATION
The AD7680 is a 16-bit, successive approximation ADC based
around a capacitive DAC. The AD7680 can convert analog
show simplified schematics of the ADC. The ADC comprises
control logic, SAR, and a capacitive DAC. Figure 11 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on the selected VIN
channel.
03643-0-004
CAPACITIVE
DAC
CONTROL
LOGIC
SAMPLING
CAPACITOR
COMPARATOR
ACQUISITION
PHASE
A
B
SW1
VDD/2
SW2
VIN
Figure 11. ADC Acquisition Phase
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(Figure 12). The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code
(see the ADC Transfer Function section).
03643-0-005
CAPACITIVE
DAC
CONTROL
LOGIC
SAMPLING
CAPACITOR
COMPARATOR
CONVERSION
PHASE
A
B
SW1
VDD/2
SW2
VIN
Figure 12. ADC Conversion Phase
ANALOG INPUT
Figure 13 shows an equivalent circuit of the analog input
structure of the AD7680. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. This causes these diodes to become
forward-biased and to start conducting current into the
substrate. The maximum current these diodes can conduct
without causing irreversible damage to the part is 10 mA.
Capacitor C1 in Figure 13 is typically about 5 pF and can be
attributed primarily to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance of a track-and-hold
switch. This resistor is typically about 25 Ω. Capacitor C2 is the
ADC sampling capacitor and has a capacitance of 25 pF
typically. For ac applications, removing high frequency
components from the analog input signal is recommended by
use of an RC low-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This may necessitate the use of
an input buffer amplifier. The choice of the op amp is a function
of the particular application. When no amplifier is used to drive
the analog input, the source impedance should be limited to low
values. The maximum source impedance depends on the
amount of total harmonic distortion (THD) that can be
tolerated. The THD increases as the source impedance
increases, and performance degrades (see Figure 8).
03643-0-006
R1
C2
25pF
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
VIN
VDD
C1
5pF
D1
D2
Figure 13. Equivalent Analog Input Circuit
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