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參數(shù)資料
| 型號(hào)： | AD7680BRMZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT LP UNIPOLR 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 26.4mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
AD7680
Rev. A | Page 16 of 24
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7680 when not
converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 19 shows how as the
throughput rate is reduced, the part remains in its shut-down
state longer, and the average power consumption over time
drops accordingly.
For example, if the AD7680 is operated in a continuous
sampling mode, with a throughput rate of 10 kSPS and an SCLK
of 2.5 MHz (VDD = 3.6 V), and the device is placed in power-
down mode between conversions, the power consumption is
calculated as follows. The maximum power dissipation during
normal operation is 6.84 mW (VDD = 3.6 V). If the power-up
time from power-down is 1 μs, and the remaining conversion
time is 8 μs, (using a 20 SCLK transfer), then the AD7680 can
be said to dissipate 6.84 mW for 9 μs during each conversion
cycle. With a throughput rate of 10 kSPS, the cycle time is 100
μs.
For the remainder of the conversion cycle, 91 μs, the part
remains in power-down mode. The AD7680 can be said to
dissipate 1.08 μW for the remaining 91 μs of the conversion
cycle. Therefore, with a throughput rate of 10 kSPS, the average
power dissipated during each cycle is
(9/100) × (6.84 mW) + (91/100) × (1.08 μW) = 0.62 mW
Figure 19 shows the power dissipation versus the throughput
rate when using the power-down mode with 3.6 V supplies, a
2.5 MHz SCLK, and a 20 SCLK serial transfer.
03643-0-012
P
O
WE
R
(mW)
0.01
0
5
10
15
20
25
THROUGHPUT (kSPS)
30
35
40
45
50
0.1
1
10
VDD = 3.6V
FSCLK = 2.5MHz
Figure 19. Power vs. Throughput Using
Power-Down Mode with 20 SCLK Transfer at 3.6 V
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