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參數(shù)資料
| 型號(hào)： | AD7684BRMZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 100KSPS DIFF 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 6mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7684CBZ-ND - BOARD EVALUATION FOR AD7684 |
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AD7684
Rev. A | Page 13 of 16
04
30
2-
02
2
AD7684
REF
GND
VDD
–IN
+IN
DCLOCK
DOUT
CS
3-WIRE INTERFACE
100nF
2.7V TO 5.25V
2.2
μF TO 10μF
(NOTE 2)
REF
0 TO VREF
33
Ω
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
VREF TO 0
33
Ω
2.7nF
(NOTE 3)
(NOTE 4)
NOTE 1: SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
NOTE 2: CREF IS USUALLY A 10μF CERAMIC CAPACITOR (X5R).
NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 22. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended application
diagram for the AD7684.
ANALOG INPUTS
The analog inputs (+IN, IN) need to be driven differentially
180° from each other, as shown in Figure 22. Holding either
input at GND or a fixed dc gives erroneous conversion results
because the AD7684 is intended for differential operation only.
For applications requiring –IN to be at GND (±100 mV), the
AD7683 should be used.
Figure 23 shows an equivalent circuit of the input structure of
the AD7684. The two diodes, D1 and D2, provide ESD protection
for the analog inputs, +IN and IN. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V because this causes these diodes to
become forward-biased and start conducting current. However,
these diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the supplies of the input buffer (U1) are different
from VDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
04302-023
CIN
RIN
D1
D2
CPIN
+IN
OR –IN
GND
VDD
Figure 23. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the differential
signal between +IN and IN. By using this differential input, small
signals common to both inputs are rejected. During the acquisition
phase, the impedance of the analog inputs can be modeled as a
parallel combination of the Capacitor CPIN and the network
formed by the series connection of RIN and CIN. CPIN is primarily
the pin capacitance. RIN is typically 600 Ω and is a lumped
component made up of some serial resistors and the on-
resistance of the switches. CIN is typically 30 pF and is mainly
the ADC sampling capacitor. During the conversion phase,
when the switches are opened, the input impedance is limited
to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces
undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7684 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7684 is easy to drive, the driver amplifier
needs to meet the following requirements:
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7684. Note that the AD7684
has a noise level much lower than most other 16-bit ADCs
and, therefore, can be driven by a noisier op amp while
preserving the same or better system performance. The
noise coming from the driver is filtered by the AD7684
analog input circuit 1-pole, low-pass filter made by RIN and
CIN or by the external filter, if one is used.
For ac applications, the driver needs to have a THD
performance commensurate with the AD7684. Figure 15
shows the THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7684 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the data sheet of the amplifier,
settling at 0.1% to 0.01% is more commonly specified. This
could differ significantly from the settling time at a 16-bit
level and should be verified prior to driver selection.
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