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參數(shù)資料
| 型號： | AD7689ACPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 250KSPS 8CH 20LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring Motor Control |
| 產(chǎn)品變化通告： | Startup Circuitry Design Improvement Change 15/April/2009 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 21mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，雙極；4 個偽差分，雙極 |
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Data Sheet
AD7682/AD7689
Rev. D | Page 29 of 32
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
to any host using an SPI, serial port, or FPGA. The connection
diagram is shown in Figure 40, and the corresponding timing
is given in Figure 41. For the SPI, the host should use CPHA =
CPOL = 0. Reading/writing spanning conversion is shown,
which covers all three modes detailed in the Digital Interface
section. For this mode, the host must generate the data transfer
based on the conversion time. For an interrupt driven transfer
that uses a busy indicator, refer to the Read/Write Spanning
Conversion with a Busy Indicator section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned high before the
safe data transfer time, tDATA, and then held high beyond the
conversion time, tCONV, to avoid generation of the busy signal
indicator.
the acquisition phase and power-down. When the host brings
CNV low after tCONV (maximum), the MSB is enabled on SDO.
The host also must enable the MSB of the CFG register at this
time (if necessary) to begin the CFG update. While CNV is low,
both a CFG update and a data readback take place. The first 14
SCK rising edges are used to update the CFG, and the first 15
SCK falling edges clock out the conversion results starting with
MSB 1. The restriction for both configuring and reading is
that they both must occur before the tDATA time of the next conver-
sion elapses. All 14 bits of CFG[13:0] must be written, or they
are ignored. In addition, if the 16-bit conversion result is not
read back before tDATA elapses, it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16th (or 30th) SCK falling edge, or
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If CFG readback is enabled, the CFG register associated with the
conversion result is read back MSB first following the LSB of the
conversion result. A total of 30 SCK falling edges is required to
return SDO to high impedance if this is enabled.
MISO
MOSI
SCK
SS
CNV
FOR SPI USE CPHA = 0, CPOL = 0.
SCK
SDO
DIN
AD7682/
AD7689
DIGITAL HOST
07
35
3-
03
6
UPDATE (n)
CFG/SDO
UPDATE (n + 1)
CFG/SDO
ACQUISITION (n)
ACQUISITION
(n + 1)
ACQUISITION
(n - 1)
MSB MSB – 1
1
2
BEGIN DATA (n – 1)
BEGIN CFG (n + 1)
CFG
MSB
CFG
MSB – 1
LSB + 1
14
15
SEE NOTE
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
16/
30
CONVERSION (n)
END DATA (n – 1)
END CFG (n + 1)
CFG
LSB
X
>
tCONV
LSB
SCK
CNV
DIN
SDO
LSB + 1
14
15
16/
30
CONVERSION (n – 1)
END DATA (n – 2)
END CFG (n)
CFG
LSB
X
tCONV
tDATA
tCNVH
tDATA
tDIS
tEN
tDSDO
tHSDO
tHDIN
tSDIN
tCLSCK
tEN
tSCK
tSCKH
tSCKL
tDIS
tCONV
LSB
07
35
3-
0
37
tACQ
tCYC
(QUIET
TIME)
(QUIET
TIME)
EOC
RETURN CNV HIGH
FOR NO BUSY
RETURN CNV HIGH
FOR NO BUSY
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