參數(shù)資料
型號(hào): AD7694BRMZRL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/16頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT SAR 250KSPS 8MSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 250k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 6.3mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個(gè)差分,單極
配用: EVAL-AD7694CBZ-ND - BOARD EVALUATION FOR AD7694
AD7694
Rev. A | Page 12 of 16
APPLICATION INFORMATION
SW+
MSB
16,384C
IN+
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
IN–
4C
2C
C
32,768C
SW–
MSB
16,384C
LSB
4C
2C
C
32,768C
05003-018
Figure 18. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7694 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of con-
verting 250,000 samples per second (250 kSPS) and powers
down between conversions. When operating at 100 SPS, for
example, it typically consumes 4 μW, ideal for battery-powered
applications.
The AD7694 provides the user with on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7694 is specified from 2.7 V to 5.25 V. It is housed in an
8-lead MSOP. The AD7694 is an improved second source to
LTC1864 and LTC1864L. For even better performance, the
AD7685 should be considered.
CONVERTER OPERATION
The AD7694 is a successive approximation ADC based on a
charge redistribution DAC. Figure 18 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase begins. When the conversion phase begins,
SW+ and SW are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Thus, the differential voltage between the inputs, IN+
and IN, captured at the end of the acquisition phase applies to
the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65536). The
control logic toggles these switches, starting with the MSB, in
order to bring the comparator back into a balanced condition.
After the completion of this process, the part returns to the
acquisition phase and the control logic generates the ADC
output code.
Because the AD7694 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7694 is shown in
000...000
000...001
000...010
111...101
111...110
111...111
ADC
CODE
(S
TRAIGHT
BINARY
)
ANALOG INPUT
+FS – 1.5 LSB
+
FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
05003-019
Figure 19. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output Code
Hexadecimal
FSR – 1 LSB
4.999924 V
FFFF1
Midscale + 1 LSB
2.500076 V
8001
Midscale
2.5 V
8000
Midscale – 1 LSB
2.499924 V
7FFF
–FSR + 1 LSB
76.3 μV
0001
–FSR
0 V
00002
1 This is also the code for an overranged analog input (VIN+ – VIN– above
VREF – VGND).
2 This is also the code for an underranged analog input (VIN+ – VIN– below VGND).
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